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superh risc engine sh7718r hardware manual ade-602-103a rev. 2.0 3/11/00 hitachi, ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi?s or any third party?s patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party?s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi?s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi?s sales office for any questions regarding this document or hitachi semiconductor products.
preface the sh7718r is a high-performance risc (reduced instruction set computer) microcomputer. it represents a new generation of microcomputer (superh* risc engine) that incorporates peripheral functions needed for system configuration while achieving the low power consumption vital to microcomputer applications. the sh7718r cpu has a risc type instruction set, in which basic instructions run at one instruction per state, creating a dramatic improvement in the speed of instruction execution. it has an on-chip floating-point unit (fpu) compliant with the ieee754 single-precision floating-point specification, enabling most fpu operations, including multiply-and-accumulate operations, to be executed by a single chip, for high precision at higher speed. the sh7718r's instructions are upward-compatible with the instructions of the sh-1, sh-2, and sh-3, facilitating migration from an sh-1, sh-2, or sh-3 to the sh7718r. the sh7718r is also fully compatible with the sh7708 series (sh7708, sh7708s, and sh7708r). to enable users to construct systems with the smallest number of parts, the sh7718r has an on- chip coprocessor as its floating point operations unit (fpu), an on-chip oscillation circuit, interrupt controller (intc), timer, real-time clock (rtc), and serial communication interface (sci) peripheral modules. a user break controller (ubc) is provided on chip to support program development and facilitate simple debugging. cache memory has been built in to increase cpu processing performance, and a memory management unit (mmu) translates 4 gbytes of virtual and physical space addresses. the efficiency of external memory accesses has been increased by a bus state controller (bsc) that supports external memory accesses. dram, synchronous dram, and pseudo-sram can be connected directly without glue logic. this manual describes the hardware of the sh7718r. for information on instructions, see the programming manual . note: * superh is a trademark of hitachi, ltd. related manual details of sh7718r execution instructions: sh-3/sh-3e/sh3-dsp programming manual contact the nearest sales office for information on the development environment system.
main revisions and additions in this edition page item revisions (see manual for details) 3 table 1.1 features hardware standby mode added to power-down modes 5 product lineup addition 7 figure 1.2 pin arrangement pin arrangement positions amended (entire figure rotated 90 so that pin 1 is at bottom left) correction of pins 107, 126, and 129 56 2.6 usage note new section added 192 10.11 notes on board design following items added: power supply pin wiring external device connection 210 11.2.3 wait state control register 1 (wcr1) bit 15 (waitsel) description added 244 11.3.3 basic interface added description of wait state timing when waitsel is set to 1 274 figure 11.30 synchronous dram auto-refresh timing rd/ wr waveform amended 302 11.4.1 when area 6 is designated for pcmcia, with a 16-bit bus width new sections added 302 11.4.2 self-refreshing 302 to 303 11.4.3 pcmcia area access 325 table 13.1 rtc pin configuration note amended 342 13.4 usage notes new section added 473 figure 17.43 synchronous dram self-refresh cycle (tpc = 0) rd/ wr signal waveform amended 549 table d.1 list of models list of models added
i contents section 1 overview .............................................................................................................. 1 1.1 sh7718r features ........................................................................................................... .. 1 1.2 block diagram.............................................................................................................. ..... 5 1.3 pin description............................................................................................................ ....... 7 1.3.1 pin arrangement................................................................................................... 7 1.3.2 sh7718r pin functions ....................................................................................... 8 section 2 cpu ....................................................................................................................... 13 2.1 organization of registers .................................................................................................. 13 2.1.1 privileged mode and banks.................................................................................. 13 2.1.2 general-purpose registers ................................................................................... 16 2.1.3 system registers................................................................................................... 18 2.1.4 control registers .................................................................................................. 19 2.2 data formats............................................................................................................... ....... 21 2.2.1 data format in registers ...................................................................................... 21 2.2.2 data format in memory ....................................................................................... 21 2.3 instruction features ....................................................................................................... .... 22 2.3.1 executing instructions .......................................................................................... 22 2.3.2 addressing modes ................................................................................................ 23 2.3.3 instruction formats............................................................................................... 28 2.4 instruction set ............................................................................................................ ........ 31 2.4.1 instruction set by classification........................................................................... 31 2.4.2 operation code map............................................................................................. 50 2.5 processing states and processing modes........................................................................... 53 2.5.1 processing states .................................................................................................. 53 2.5.2 processing mode................................................................................................... 55 2.6 usage note................................................................................................................. ........ 56 section 3 floating point unit ........................................................................................... 57 3.1 introduction............................................................................................................... ......... 57 3.2 floating point registers and system registers for fpu ................................................... 58 3.2.1 floating point register file .................................................................................. 58 3.2.2 floating point communication register (fpul)................................................. 58 3.2.3 floating point status/control register (fpscr) ................................................. 58 3.3 floating point format ...................................................................................................... .. 60 3.3.1 floating point format........................................................................................... 60 3.3.2 not a number (nan) ............................................................................................ 60 3.3.3 denormalized values ........................................................................................... 61 3.3.4 other special values ............................................................................................ 61
ii 3.4 floating point exception model ........................................................................................ 62 3.4.1 enabled exception ................................................................................................ 62 3.4.2 disabled exception............................................................................................... 62 3.4.3 exception event and code for fpu ..................................................................... 62 3.4.4 alignment of floating point data in memory ..................................................... 63 3.4.5 arithmetic with special operands........................................................................ 63 3.5 synchronization issues..................................................................................................... .. 6 3 section 4 memory management unit (mmu) ............................................................ 65 4.1 overview................................................................................................................... ......... 65 4.1.1 features................................................................................................................. 65 4.1.2 function ................................................................................................................ 6 5 4.1.3 the sh7718r mmu ............................................................................................ 67 4.1.4 register configuration ......................................................................................... 69 4.2 description of registers................................................................................................... .. 7 0 4.3 tlb functions .............................................................................................................. ..... 72 4.3.1 tlb structure....................................................................................................... 72 4.3.2 creating tlb index numbers .............................................................................. 74 4.3.3 tlb address comparison .................................................................................... 75 4.3.4 page management information............................................................................. 76 4.4 mmu functions.............................................................................................................. ... 77 4.4.1 mmu hardware management ............................................................................. 77 4.4.2 mmu software management............................................................................... 78 4.4.3 mmu instructions (ldtlb)................................................................................ 78 4.4.4 avoiding synonym problems............................................................................... 80 4.5 mmu exceptions............................................................................................................. .. 8 1 4.5.1 tlb miss .............................................................................................................. 81 4.5.2 tlb protection violation ..................................................................................... 82 4.5.3 tlb invalid exception ......................................................................................... 83 4.5.4 initial page write.................................................................................................. 84 4.5.5 processing when an mmu exception occurs ...................................................... 87 4.6 memory-mapped tlb....................................................................................................... 88 4.6.1 address array....................................................................................................... 88 4.6.2 data array............................................................................................................. 89 4.6.3 examples............................................................................................................... 90 4.7 cautions ................................................................................................................... .......... 91 section 5 exception processing ....................................................................................... 93 5.1 overview................................................................................................................... ......... 93 5.1.1 features................................................................................................................. 93 5.1.2 register configuration ......................................................................................... 93 5.2 exception processing function.......................................................................................... 93 5.2.1 exception processing flow................................................................................... 93
iii 5.2.2 exception processing vector table...................................................................... 94 5.2.3 receiving interrupt causes................................................................................... 96 5.2.4 exception codes................................................................................................... 98 5.2.5 exception requests and bl bits .......................................................................... 99 5.2.6 returning from exception processing .................................................................. 100 5.3 register description....................................................................................................... .... 100 5.4 exception handler operation ............................................................................................ 101 5.4.1 reset .................................................................................................................... . 101 5.4.2 interrupts............................................................................................................... 101 5.4.3 general exceptions............................................................................................... 101 5.5 individual exception operations ....................................................................................... 102 5.5.1 resets................................................................................................................... . 102 5.5.2 general exceptions............................................................................................... 103 5.5.3 interrupts............................................................................................................... 1 07 5.6 cautions ................................................................................................................... .......... 107 section 6 cache ..................................................................................................................... 109 6.1 overview................................................................................................................... ......... 109 6.1.1 features................................................................................................................. 109 6.1.2 cache structure..................................................................................................... 109 6.1.3 register configuration ......................................................................................... 111 6.2 register description....................................................................................................... .... 111 6.2.1 cache control register (ccr)............................................................................. 111 6.3 cache operation............................................................................................................ ..... 112 6.3.1 searching the cache ............................................................................................. 112 6.3.2 read access.......................................................................................................... 113 6.3.3 write access......................................................................................................... 114 6.3.4 write-back buffer ................................................................................................ 114 6.3.5 coherency of cache and external memory ......................................................... 115 6.3.6 ram mode........................................................................................................... 115 6.4 memory-mapped cache .................................................................................................... 115 6.4.1 address array....................................................................................................... 115 6.4.2 data array ............................................................................................................ 116 6.4.3 examples............................................................................................................... 11 8 section 7 interrupt controller (intc) ........................................................................... 119 7.1 overview................................................................................................................... ......... 119 7.1.1 features................................................................................................................. 119 7.1.2 block diagram...................................................................................................... 120 7.1.3 pin configuration ................................................................................................. 121 7.1.4 register configuration ......................................................................................... 121 7.2 interrupt causes ........................................................................................................... ...... 121 7.2.1 nmi interrupts ...................................................................................................... 122
iv 7.2.2 irl interrupts ....................................................................................................... 122 7.2.3 on-chip peripheral module interrupts................................................................. 123 7.2.4 interrupt exception processing and priority......................................................... 124 7.3 register descriptions...................................................................................................... ... 128 7.3.1 interrupt priority registers a and b (ipra, iprb) ............................................. 128 7.3.2 interrupt control register (icr) .......................................................................... 129 7.4 operation .................................................................................................................. ......... 130 7.4.1 interrupt sequence ................................................................................................ 130 7.4.2 multiple interrupts ................................................................................................ 132 7.5 interrupt response ......................................................................................................... .... 132 section 8 user break controller (ubc) ........................................................................ 135 8.1 overview................................................................................................................... ......... 135 8.1.1 features................................................................................................................. 135 8.1.2 block diagram...................................................................................................... 135 8.1.3 register set........................................................................................................... 13 7 8.1.4 setting break conditions and registers ............................................................... 137 8.2 register descriptions...................................................................................................... ... 139 8.2.1 break address registers (bara and barb) ..................................................... 139 8.2.2 break address space identification registers a and b (basra and basrb). 139 8.2.3 break address mask register a (bamra) ........................................................ 140 8.2.4 break address mask register b (bamrb)......................................................... 141 8.2.5 break bus cycle register a (bbra) .................................................................. 141 8.2.6 break bus cycle register b (bbrb)................................................................... 142 8.2.7 break b data register (bdrb) ........................................................................... 143 8.2.8 break b data mask register (bdmrb) .............................................................. 144 8.2.9 break control register (brcr)........................................................................... 145 8.3 operation .................................................................................................................. ......... 147 8.3.1 flow of the user break operation........................................................................ 147 8.3.2 break on instruction fetch cycle ......................................................................... 147 8.3.3 break on data access cycle................................................................................. 148 8.3.4 program counter (pc) values saved ................................................................... 149 8.3.5 examples............................................................................................................... 14 9 8.3.6 cautions ................................................................................................................ 1 52 section 9 power-down modes ......................................................................................... 153 9.1 overview................................................................................................................... ......... 153 9.1.1 power-down modes............................................................................................. 153 9.1.2 register configuration ......................................................................................... 154 9.1.3 pin configuration ................................................................................................. 155 9.2 register description....................................................................................................... .... 155 9.2.1 standby control register (stbcr) ..................................................................... 155 9.3 sleep mode ................................................................................................................. ....... 157
v 9.3.1 transition to sleep mode ..................................................................................... 157 9.3.2 canceling sleep mode.......................................................................................... 157 9.4 standby mode ............................................................................................................... ..... 157 9.4.1 transition to standby mode ................................................................................. 157 9.4.2 canceling standby mode ..................................................................................... 158 9.4.3 clock pause function ........................................................................................... 159 9.5 module standby function.................................................................................................. 15 9 9.5.1 transition to module standby function............................................................... 159 9.5.2 clearing the module standby function................................................................ 160 9.6 timing of status pin changes ...................................................................................... 160 9.6.1 timing for resets ................................................................................................. 160 9.6.2 timing for canceling standbys ............................................................................ 162 9.6.3 timing for canceling sleep mode ....................................................................... 163 9.7 hardware standby mode ................................................................................................... 165 9.7.1 transition to hardware standby mode................................................................. 165 9.7.2 canceling hardware standby mode..................................................................... 166 9.7.3 hardware standby mode timing ......................................................................... 166 section 10 on-chip oscillation circuits ....................................................................... 169 10.1 overview.................................................................................................................. .......... 169 10.1.1 features................................................................................................................ . 169 10.2 overview of the cpg....................................................................................................... .. 170 10.2.1 cpg block diagram............................................................................................. 170 10.2.2 cpg pin configuration......................................................................................... 172 10.2.3 cpg register configuration................................................................................. 172 10.3 clock operating modes..................................................................................................... 173 10.4 register descriptions..................................................................................................... .... 179 10.4.1 frequency control register (frqcr)................................................................. 179 10.5 changing the frequency .................................................................................................... 182 10.5.1 changing the multiplication rate......................................................................... 182 10.5.2 changing the division ratio ................................................................................ 182 10.6 pll standby function...................................................................................................... . 183 10.6.1 overview of the pll standby function............................................................... 183 10.6.2 usage ................................................................................................................... . 183 10.7 controlling clock output .................................................................................................. 184 10.7.1 clock modes 0?.................................................................................................. 184 10.7.2 clock modes 3 and 4 ............................................................................................ 184 10.8 overview of the watchdog timer (wdt)......................................................................... 185 10.8.1 block diagram of the wdt ................................................................................. 185 10.8.2 register configurations ........................................................................................ 185 10.9 wdt registers............................................................................................................. ...... 186 10.9.1 watchdog timer counter (wtcnt) ................................................................... 186 10.9.2 watchdog timer control/status register (wtcsr) ........................................... 186
vi 10.9.3 notes on register access ..................................................................................... 188 10.10 using the wdt ............................................................................................................ ...... 189 10.10.1 canceling standbys .............................................................................................. 189 10.10.2 changing the frequency....................................................................................... 189 10.10.3 using watchdog timer mode .............................................................................. 190 10.10.4 using interval timer mode .................................................................................. 190 10.11 notes on board design .................................................................................................... .. 190 section 11 bus state controller (bsc) ......................................................................... 193 11.1 overview.................................................................................................................. .......... 193 11.1.1 features................................................................................................................ . 193 11.1.2 block diagram...................................................................................................... 194 11.1.3 pin configuration ................................................................................................. 196 11.1.4 register configuration............................................................................................ 198 11.1.5 area overview...................................................................................................... 199 11.1.6 pcmcia support ................................................................................................. 202 11.2 ..bsc registers ........................................................................................................... ......... 206 11.2.1 bus control register 1 (bcr1)............................................................................ 206 11.2.2 bus control register 2 (bcr2)............................................................................ 209 11.2.3 wait state control register 1 (wcr1) ................................................................ 210 11.2.4 wait state control register 2 (wcr2) ................................................................ 211 11.2.5 individual memory control register (mcr)....................................................... 215 11.2.6 dram control register (dcr)........................................................................... 219 11.2.7 pcmcia control register (pcr) ........................................................................ 221 11.2.8 synchronous dram mode register (sdmr)..................................................... 222 11.2.9 refresh timer control/status register (rtcsr) ................................................ 223 11.2.10 refresh timer counter (rtcnt) ........................................................................ 225 11.2.11 refresh time constant register (rtcor).......................................................... 226 11.2.12 refresh count register (rfcr)........................................................................... 226 11.2.13 cautions on accessing refresh control related registers.................................. 227 11.3 bsc operation............................................................................................................. ...... 228 11.3.1 endian/access size and data alignment ............................................................. 228 11.3.2 description of areas............................................................................................. 234 11.3.3 basic interface ...................................................................................................... 237 11.3.4 dram interface................................................................................................... 245 11.3.5 synchronous dram interface ............................................................................. 261 11.3.6 pseudo-sram direct connection ....................................................................... 277 11.3.7 burst rom interface ............................................................................................ 286 11.3.8 pcmcia interface................................................................................................ 289 11.3.9 waits between access cycles .............................................................................. 301 11.3.10 bus arbitration ..................................................................................................... 302 11.4 usage notes ............................................................................................................... ........ 303 11.4.1 when area 6 is designated for pcmcia, with a 16-bit bus width................... 303
vii 11.4.2 self-refreshing..................................................................................................... 303 11.4.3 pcmcia area access.......................................................................................... 303 section 12 timer (tmu) ................................................................................................... 305 12.1 overview.................................................................................................................. .......... 305 12.1.1 features................................................................................................................ . 305 12.1.2 block diagram...................................................................................................... 305 12.1.3 pin configuration ................................................................................................. 307 12.1.4 register configuration ......................................................................................... 307 12.2 tmu registers............................................................................................................. ...... 308 12.2.1 timer output control register (tocr)............................................................... 308 12.2.2 timer start register (tstr) ................................................................................ 309 12.2.3 timer control register (tcr) ............................................................................. 310 12.2.4 timer constant register (tcor)......................................................................... 313 12.2.5 timer counters (tcnt)....................................................................................... 313 12.2.6 input capture register (tcpr2) .......................................................................... 315 12.3 tmu operation ............................................................................................................. .... 316 12.3.1 overview............................................................................................................... 3 16 12.3.2 basic functions..................................................................................................... 316 12.4 interrupts ................................................................................................................ ............ 320 12.4.1 status flag set timing ......................................................................................... 320 12.4.2 status flag clear timing ...................................................................................... 321 12.4.3 interrupt sources and priorities ............................................................................ 321 12.5 usage notes ............................................................................................................... ........ 322 12.5.1 writing to registers.............................................................................................. 322 12.5.2 reading registers................................................................................................. 322 section 13 realtime clock (rtc) ................................................................................... 323 13.1 overview.................................................................................................................. .......... 323 13.1.1 features................................................................................................................ . 323 13.1.2 block diagram...................................................................................................... 323 13.1.3 pin configuration ................................................................................................. 325 13.1.4 rtc register configuration................................................................................. 326 13.2 rtc registers............................................................................................................. ....... 326 13.2.1 64-hz counter (r64cnt) .................................................................................... 326 13.2.2 second counter (rseccnt)............................................................................... 327 13.2.3 minute counter (rmincnt)............................................................................... 327 13.2.4 hour counter (rhrcnt) .................................................................................... 328 13.2.5 day of the week counter (rwkcnt) ................................................................ 328 13.2.6 date counter (rdaycnt).................................................................................. 329 13.2.7 month counter (rmoncnt) .............................................................................. 330 13.2.8 year counter (ryrcnt)..................................................................................... 330 13.2.9 second alarm register (rsecar)...................................................................... 331
viii 13.2.10 minute alarm register (rminar) ..................................................................... 331 13.2.11 hour alarm register (rhrar)........................................................................... 332 13.2.12 day of the week alarm register (rwkar)....................................................... 332 13.2.13 date alarm register (rdayar)......................................................................... 333 13.2.14 month alarm register (rmonar)..................................................................... 334 13.2.15 rtc control register 1 (rcr1) .......................................................................... 334 13.2.16 rtc control register 2 (rcr2) .......................................................................... 336 13.3 rtc operation............................................................................................................. ...... 337 13.3.1 initial settings of registers after power-on......................................................... 337 13.3.2 setting the time ................................................................................................... 337 13.3.3 reading the time ................................................................................................. 339 13.3.4 alarm function..................................................................................................... 340 13.3.5 crystal resonator circuit ..................................................................................... 341 13.4 usage notes ............................................................................................................... ........ 342 13.4.1 register writes during rtc count ...................................................................... 342 section 14 serial communication interface (sci) ..................................................... 343 14.1 overview.................................................................................................................. .......... 343 14.1.1 features................................................................................................................ . 343 14.1.2 block diagram...................................................................................................... 344 14.1.3 pin configuration ................................................................................................. 345 14.1.4 register configuration ......................................................................................... 345 14.2 register descriptions..................................................................................................... .... 346 14.2.1 receive shift register (scrsr) .......................................................................... 346 14.2.2 receive data register (scrdr).......................................................................... 346 14.2.3 transmit shift register (sctsr)......................................................................... 346 14.2.4 transmit data register (sctdr) ........................................................................ 347 14.2.5 serial mode register (scsmr) ........................................................................... 347 14.2.6 serial control register (scscr) ......................................................................... 350 14.2.7 serial status register (scssr) ............................................................................ 353 14.2.8 serial port register (scsptr)............................................................................. 357 14.2.9 bit rate register (scbrr) .................................................................................. 358 14.3 operation ................................................................................................................. .......... 366 14.3.1 overview............................................................................................................... 3 66 14.3.2 operation in asynchronous mode........................................................................ 368 14.3.3 multiprocessor communication ........................................................................... 378 14.3.4 synchronous operation ........................................................................................ 386 14.4 sci interrupt sources..................................................................................................... .... 395 14.5 usage notes ............................................................................................................... ........ 395 section 15 smart card interface ...................................................................................... 399 15.1 overview.................................................................................................................. .......... 399 15.1.1 features................................................................................................................ . 399
ix 15.1.2 block diagram...................................................................................................... 400 15.1.3 pin configuration ................................................................................................. 401 15.1.4 register configuration ......................................................................................... 401 15.2 register descriptions..................................................................................................... .... 401 15.2.1 smart card mode register (scscmr) ............................................................... 402 15.2.2 serial status register (scssr) ............................................................................ 403 15.3 operation ................................................................................................................. .......... 404 15.3.1 overview............................................................................................................... 4 04 15.3.2 pin connections .................................................................................................... 405 15.3.3 data format .......................................................................................................... 406 15.3.4 register settings................................................................................................... 407 15.3.5 clock................................................................................................................... .. 409 15.3.6 data transmission and reception ........................................................................ 412 15.4 usage notes ............................................................................................................... ........ 418 15.4.1 receive data timing and receive margin in asynchronous mode .................... 418 15.4.2 retransmission (receive and transmit modes)................................................... 420 section 16 i/o ports ............................................................................................................. 423 16.1 overview.................................................................................................................. .......... 423 16.1.1 features................................................................................................................ . 423 16.1.2 block diagram...................................................................................................... 423 16.1.3 pin configuration ................................................................................................. 426 16.1.4 register configuration ......................................................................................... 427 16.2 register descriptions..................................................................................................... .... 427 16.2.1 port control register (pctr) .............................................................................. 427 16.2.2 port data register (pdtr)................................................................................... 428 16.2.3 serial port register (scsptr)............................................................................. 429 section 17 electrical characteristics .............................................................................. 431 17.1 absolute maximum ratings .............................................................................................. 431 17.2 dc characteristics ........................................................................................................ ..... 432 17.3 ac characteristics ........................................................................................................ ..... 433 17.3.1 clock timing ........................................................................................................ 434 17.3.2 control signal timing .......................................................................................... 440 17.3.3 ac bus timing specifications............................................................................. 444 17.3.4 basic timing......................................................................................................... 448 17.3.5 burst rom timing............................................................................................... 451 17.3.6 dram timing ..................................................................................................... 454 17.3.7 synchronous dram timing ............................................................................... 464 17.3.8 pseudo-sram timing ......................................................................................... 475 17.3.9 pcmcia timing .................................................................................................. 480 17.3.10 peripheral module signal timing ........................................................................ 487 17.3.11 ac characteristics test conditions ..................................................................... 490
x appendix a pin functions ................................................................................................. 491 a.1 pin states ................................................................................................................. .......... 491 a.2 pin specifications......................................................................................................... ...... 494 a.3 handling of unused pins ................................................................................................... 4 97 a.4 pin states in access to each address space ..................................................................... 498 appendix b control registers ......................................................................................... 534 b.1 register address map....................................................................................................... . 534 b.2 register bit list.......................................................................................................... ....... 538 b.3 register states in reset and power-down states .............................................................. 544 appendix c load time variation due to load capacitance ................................. 548 appendix d list of models ............................................................................................... 549 appendix e package dimensions ................................................................................... 550
1 section 1 overview 1.1 sh7718r features the sh7718r is a 32-bit risc (reduced instruction set computer) microprocessor. its object code is up-ward compatible with the sh-1 and sh-2 and fully pin compatible with sh7708 series (sh7708, sh7708s, sh7708r). it has a built-in single precision floating point operations unit (fpu) and a memory management unit (mmu) that has an 8-kbyte cache that can be used for write-back or write-through and a 128-entry, 4-way set-associative translation lookaside buffer (tlb). the sh7718r has an on-chip bus state controller (bsc) and can be connected directly to dram, synchronous dram (sdram), and pseudo-sram (psram) without external circuits. the length of sh7718r instructions is fixed to 16 bits, so the code size can be almost cut in half compared to programs that use 32-bit instructions. the features of the sh7718r are listed in table 1.1.
2 table 1.1 sh7718r features item features cpu ? original hitachi superh architecture ? 32-bit internal data bus ? general-register files ? sixteen 32-bit general registers (eight 32-bit shadow registers) ? five 32-bit control registers ? six 32-bit system registers ? risc-type instruction set (downward compatibility with the sh-1 and sh-2 series ) ? instruction length: 16-bit fixed length for improved code efficiency ? load-store architecture ? delayed branch instructions ? instruction set based on c language ? instruction execution time: one instruction/cycle for basic instructions ? logical address space: 4 gbytes (448-mbyte actual memory space) ? space identifier asid: 8 bits, 256 logical address space ? on-chip multiplier ? five-stage pipeline fpu ? superh architecture coprocessor ? supports single precision floating-point format ? supports subset of the ieee754 standard data type ? supports invalid-operation and division-by-zero exceptions (subset of the ieee754 standard ) ? supports rounding to zero (subset of the ieee754 standard ) ? sixteen 32-bit floating-point data registers ? supports fmac (multiply & accumulate) ? supports fdiv/fsqrt (division/square root instructions) ? supports fldi0/fldi1 (load constant0/1) ? instruction latency time: two cycles for fmac/fadd/fsub/fmul ? execution pitch: one cycle for fmac/fadd/fsub/fmul
3 table 1.1 sh7718r features (cont) item features operating modes, clock pulse generator ? clock mode: selected from an on-chip oscillator module, a frequency- doubling circuit, or a clock output by combining with pll synchronization circuit ? processing states: ? power-on reset state ? manual reset state ? exception processing state ? program execution state ? power-down state ? bus-released state ? power-down modes: ? sleep mode ? standby mode ? hardware standby mode ? on-chip clock pulse generator ? watchdog timer: 1 channel memory management unit ? 4 gbytes of address space, 256 address spaces (asid 8 bits) ? supports single virtual memory mode and multiplexed virtual memory mode ? page unit sharing ? supports multiple page sizes: 1, 4 kbytes ? 128-entry, 4-way set associative tlb ? supports software selection of replacement way and random-replacement algorithms ? contents of tlb are directly accessible by address mapping cache memory ? mixed instruction/data ? selectable operating modes: ? normal mode (8 kbytes cache) ? ram mode (4-kbyte cache and 4-kbyte ram) ? 128 entries, 16-byte block length ? 4-way set associative (8-kbyte cache) ? 2-way set associative (4-kbyte cache)
4 table 1.1 sh7718r features (cont) item features cache memory (cont) ? selectable write policy (write-back/write-through), least recently used (lru) replacement algorithm ? 1-stage write-back buffer ? contents of cache memory can be accessed directly by address mapping (can be used as on-chip memory) interrupt controller ? five external interrupt pins (nmi, irl0 - irl3 ) and encoded input of 15 external interrupt causes (through irl0 - irl3 pins) ? on-chip peripheral interrupts: set priority levels for each module user break controller ? supports debugging by user break interrupts ? 2 break channels ? addresses, data values, type of access, and data size can all be set as break conditions ? supports a sequential break function bus state controller ? supports external memory access ? 32/16/8-bit external data bus ? physical address space divided into seven areas, each 64 mbytes, with the following features settable for each area: ? bus size (8, 16, or 32 bits) ? number of wait cycles (also supports a hardware wait function) ? setting the type of space enables direct connection to dram, sdram, psram, and burst rom ? dram supports fast-page mode and edo ? supports pcmcia interface ? outputs chip select signal (cs0?s6) for corresponding area ? dram/sdram refresh function ? programmable refresh interval ? supports cas-before-ras refresh and self-refresh modes ? dram/sdram/psram burst access function ? configurable as either big or little endian machine
5 table 1.1 sh7718r features (cont) item features timer ? 3-channel auto-reload type 32-bit timer ? input capture function ? 6 types of counter input clocks can be selected ? maximum resolution: 2 mhz real-time clock ? built-in clock and calendar functions ? on-chip 32-khz crystal oscillator circuit with a maximum resolution (cycle interrupt) of 1/256 second serial communi- cation interface ? select start-stop sync mode or clock sync system ? full-duplex communication ? supports smart card interface product lineup abbr. voltage operating frequency mask version model package sh7718r 3.15 v to 3.6 v 100 mhz HD6417718Rf100 144-pin plastic a-mask HD6417718Rf100a lqfp (fp-144f) 1.2 block diagram figure 1.1 is a functional block diagram of the sh7718r.
6 multiplier mmu (memory management unit) mixed instruction/ data tlb cache controller mixed instruction/ data cache memory cpu fpu interrupt controller user break controller, 2 channels bus state controller clock pulse generator with built-in pll external bus interface sci (serial communication interface) timer (3 channels) operation mode controller realtime clock peripheral address bus 16-bit peripheral data bus 32-bit logical address bus 32-bit physical address bus 32-bit data bus 32-bit data bus wdt (watchdog timer) i/o ports figure 1.1 sh7718r block diagram
7 1.3 pin description 1.3.1 pin arrangement figure 1.2 shows the pin arrangement. cs6 ce1b rd frame wr ce2a ce2b * 1 status0 status1 back irqout iois16 irl0 irl1 irl2 irl3 bs reset breq cs5 ce1a cs4 cs3 cs2 cs1 cs0 we3 iciowr we2 iciord cashh cas2h cashl cas2l we1 we0 caslh casll cas oe ras ce ras2 wait * 2 xtal2 extal2 vss (rtc) * 2 vcc d31 d30 d29 d28 vss vss (pll2) * 3 (pll2) * 3 (pll1) * 3 (pll1) * 3 110 120 130 140 144 notes: 1. leave unconnected. 2. power supply pins for the on-chip rtc oscillator. these pins must be connected to the power supply even when the rtc is not used. 3. power supply pins for the on-chip pll oscillator. these pins must be connected to the power supply even when the pll is used only in hardware standby mode. figure 1.2 pin arrangement
8 1.3.2 sh7718r pin functions table 1.2 shows the pin functions. table 1.2 sh7718r pin functions no. terminal i/o description 1 d27 i/o data bus/port 2 d26 i/o data bus/port 3 d25 i/o data bus/port 4 d24 i/o data bus/port 5 d23/port7 i/o data bus/port 6v ss power power (0 v) 7v cc power power (3.3 v) 8 d22/port6 i/o data bus/port 9 d21/port5 i/o data bus/port 10 d20/port4 i/o data bus/port 11 d19/port3 i/o data bus/port 12 d18/port2 i/o data bus/port 13 d17/port1 i/o data bus/port 14 d16/port0 i/o data bus/port 15 d15 i/o data/address bus 16 d14 i/o data/address bus 17 v ss power power (0 v) 18 v cc power power (3.3 v) 19 v ss power power (0 v) 20 v cc power power (3.3 v) 21 d13 i/o data bus 22 d12 i/o data bus 23 d11 i/o data bus 24 d10 i/o data bus 25 d9 i/o data bus 26 d8 i/o data bus 27 d7 i/o data bus 28 d6 i/o data bus 29 d5 i/o data bus
9 table 1.2 sh7718r pin functions (cont) no. terminal i/o description 30 v ss power power (0 v) 31 v cc power power (3.3 v) 32 d4 i/o data bus 33 d3 i/o data bus 34 d2 i/o data bus 35 d1 i/o data bus 36 d0 i/o data bus 37 a0 o address bus 38 a1 o address bus 39 a2 o address bus 40 a3 o address bus 41 v ss power power (0 v) 42 v cc power power (3.3 v) 43 a4 o address bus 44 a5 o address bus 45 a6 o address bus 46 a7 o address bus 47 a8 o address bus 48 a9 o address bus 49 v ss power power (0 v) 50 v cc power power (3.3 v) 51 a10 o address bus 52 a11 o address bus 53 a12 o address bus 54 v ss power power (0 v) 55 v cc power power (3.3 v) 56 a13 o address bus 57 a14 o address bus 58 a15 o address bus 59 v ss power power (0 v) 60 v cc power power (3.3 v)
10 table 1.2 sh7718r pin functions (cont) no. terminal i/o description 61 a16 o address bus 62 a17 o address bus 63 a18 o address bus 64 a19 o address bus 65 a20 o address bus 66 a21 o address bus 67 a22 o address bus 68 v ss power power (0 v) 69 v cc power power (3.3 v) 70 a23 o address bus 71 a24 o address bus 72 a25 o address bus 73 v ss (pll1)* 2 power power (0 v) for pll1 74 cap1 o external capacitance pin for pll 75 v cc (pll1)* 2 power power (3.3 v) for pll1 76 v ss (pll2)* 2 power power (0 v) for pll2 77 cap2 o external capacitance pin for pll 78 v cc (pll2)* 2 power power (3.3 v) for pll2 79 extal i external clock/crystal oscillator pin 80 xtal o crystal oscillator pin 81 ca i chip active 82 v ss power power (0 v) 83 v cc power power (3.3 v) 84 md2/rxd i operating mode pin/serial data input 85 md1/txd i/o operating mode pin/serial data output 86 md0/sck i/o operating mode pin/serial clock 87 breq reset irl3 irl2
11 table 1.2 sh7718r pin functions (cont) no. terminal i/o description 92 irl1 irl0 iois16 irqout back ce2b ce2a bs wr rd cs6 ce1b cs5 ce1a cs4 cs3 cs2 cs1 cs0 we3 iciowr d24 selection signal/io write 118 we2 iciord d16 selection signal/io read 119 cashh cas2h d24/d15 d8 selection signal 120 cashl cas2l d16/d7 d0 selection signal 121 v ss power power (0 v) 122 v cc power power (3.3 v)
12 table 1.2 sh7718r pin functions (cont) no. terminal i/o description 123 we1 d8 selection signal 124 we0 d0 selection signal 125 caslh d8 selection signal 126 casll cas oe d0 selection/memory selection signal 127 v ss power power (0 v) 128 v cc power power (3.3 v) 129 ras ce ras2 wait
13 section 2 cpu 2.1 organization of registers 2.1.1 privileged mode and banks processing modes : the sh7718r has two operating modes: user mode and privileged mode. the sh7718r operates in user mode under normal conditions and enters privileged mode in response to an exception or interrupt. there are three types of registers: general, system, and control. all of these registers are 32 bits. which registers can be accessed through software depends on the processing mode. general-purpose registers : there are 16 general-purpose registers, numbered r0 through r15. general-purpose registers r0 to r7 are banked registers that are switched by the processor mode. in privileged mode, the register bank (rb) bit in the status register (sr) defines which banked registers can be accessed as general-purpose registers and which cannot. inaccessible registers can be accessed through the load control register (ldc) and store control register (stc) instructions. when the rb bit is one (bank1 is selected), bank1 general-purpose registers r0_bank1 through r7_bank1 and non-banked general-purpose registers r8 through r15 (a total of 16 registers) can be accessed as general-purpose registers r0 through r15 and bank0 general- purpose registers r0_bank0 through r7_bank0 (eight registers) are accessed by the ldc and stc instructions. when the rb bit is a zero (bank0 is selected), bank0 general-purpose registers r0_bank0 through r7_bank0 and nonbanked general-purpose registers r8 through r15 (16 registers) can be accessed as general-purpose registers r0 through r15 and bank1 general-purpose registers r0_bank1 through r7_bank1 (eight registers) are accessed by the ldc and stc instructions. in user mode, bank0 general-purpose registers r0_bank0 through r7_bank0 and nonbanked general-purpose registers r8 through r15 can be accessed as general-purpose registers r0 through r15 (a total of 16 registers) and bank1 general-purpose registers r0_bank1 through r7_bank1 (eight registers) cannot be accessed. control registers : the control registers include registers that can be accessed in either mode (the global base register (gbr) and status register (sr)) and registers that can only be accessed in privileged mode (the saved status register (ssr), saved program counter (spc), and vector base register (vbr)). some bits in the status register (for example, the rb bit) can only be accessed in privileged mode.
14 system registers : there are four system registers that can be accessed in either processing mode: ? multiply and accumulate registers ? multiply and accumulate high (mach) ? multiply and accumulate low (macl) ? procedure register (pr) ? program counter (pc) the register configurations are shown in figure 2.1 by processing mode. switch between user and privileged modes using the processing operation mode bit in the status register.
15 r0_bank0* 1 , * 2 r1_bank0* 2 r2_bank0* 2 r3_bank0* 2 r4_bank0* 2 r5_bank0* 2 r6_bank0* 2 r7_bank0* 2 r8 r9 r10 r11 r12 r13 r14 r15 31 a. user mode programming model fr0* 5 fr1* 5 fr2* 5 fr3* 5 fr4* 5 fr5* 5 fr6* 5 fr7* 5 fr8* 5 fr9* 5 fr10* 5 fr11* 5 fr12* 5 fr13* 5 fr14* 5 fr15* 5 sr fpscr* 5 pc gbr mach macl fpul* 5 pr r0_bank1* 1 , * 3 r1_bank1* 3 r2_bank1* 3 r3_bank1* 3 r4_bank1* 3 r5_bank1* 3 r6_bank1* 3 r7_bank1* 3 r8 r9 r10 r11 r12 r13 r14 r15 31 0 r0_bank0* 1 , * 4 r1_bank0* 4 r2_bank0* 4 r3_bank0* 4 r4_bank0* 4 r5_bank0* 4 r6_bank0* 4 r7_bank0* 4 r8 r9 r10 r11 r12 r13 r14 r15 fr0* 5 fr1* 5 fr2* 5 fr3* 5 fr4* 5 fr5* 5 fr6* 5 fr7* 5 fr8* 5 fr9* 5 fr10* 5 fr11* 5 fr12* 5 fr13* 5 fr14* 5 fr15* 5 fr0* 5 fr1* 5 fr2* 5 fr3* 5 fr4* 5 fr5* 5 fr6* 5 fr7* 5 fr8* 5 fr9* 5 fr10* 5 fr11* 5 fr12* 5 fr13* 5 fr14* 5 fr15* 5 31 0 0 sr fpscr* 5 pc spc gbr mach macl fpul* 5 pr vbr b. privileged mode programming model (rb = 1) c. privileged mode programming model (rb = 0) r0_bank0* 1 , * 4 r1_bank0* 4 r2_bank0* 4 r3_bank0* 4 r4_bank0* 4 r5_bank0* 4 r6_bank0* 4 r7_bank0* 4 sr ssr ssr fpscr* 5 pc spc gbr mach macl fpul* 5 pr vbr r0_bank1* 1 , * 3 r1_bank1* 3 r2_bank1* 3 r3_bank1* 3 r4_bank1* 3 r5_bank1* 3 r6_bank1* 3 r7_bank1* 3 notes: 1. 2. 3. 4. 5. r0 functions as an index register in the indexed register- indirect addressing mode and indexed gbr-indirect addressing mode. banked register. banked register. accessible as general-purpose register when sr, rb is 1. accessible by ldc or stc instruction when sr, rb is 0. banked register. accessible as general-purpose register when sr, rb is 0. accessible by ldc or stc instruction when sr, rb is 1. fpu register. for more information, see section 3, floating point unit. figure 2.1 register configurations for different processing modes
16 table 2.1 shows the register values after a reset. table 2.1 initial register values register type register initial value* 1 general purpose r0?15 undefined fr0?r15* 2 undefined control sr md bit is 1, rb bit is 1, bl bit is 1, bits 13?0 are 1111 (h'f), reserved bits are 0, and all others are undefined gbr, ssr, spc undefined vbr h'00000000 system mach, macl, pr, fpscr* 2 , fpul* 2 undefined pc h'a0000000 notes: 1. initialized by a power-on reset or manual reset. 2. there registers are used in floating point operations. for more information on fr0 to fr15, fpscr, and fpul, see section 3, floating point unit. 2.1.2 general-purpose registers there are 16 general-purpose registers, numbered r0?15. r0?7 are banked registers. different banks of r0?7 registers (r0_bank0 through r7_bank0 and r0_bank1 through r7_bank1) are accessible in different modes (figure 2.1). figure 2.2 shows the structure of the general-purpose registers.
17 r0* 1 , * 2 r1* 2 r2* 2 r3* 2 r4* 2 r5* 2 r6* 2 r7* 2 r8 r9 r10 r11 r12 r13 r14 r15 31 0 notes: 1. 2. 3. r0 functions as an index register in the indexed register-indirect addressing mode and indexed gbr-indirect addressing mode. in some instructions, only r0 can be used as the source or destination register. r0 r7 are banked registers. in privileged mode, the sr register s rb bit determines which banks are accessed as general-purpose registers(r1_bank0 through r7_bank0 and r1_bank1 through r7_bank1). in some instructions, r0 is fixed as the source of the destination register. see section 3, floating point unit, for more information on floating point registers fr0 fr15. fr0* 3 fr1* 3 fr2* 3 fr3* 3 fr4* 3 fr5* 3 fr6* 3 fr7* 3 fr8* 3 fr9* 3 fr10* 3 fr11* 3 fr12* 3 fr13* 3 fr14* 3 fr15* 3 31 0 general-purpose registers undefined after reset floating point data register the fmac instruction uses fr0 to set the multipli- cation value. figure 2.2 structure of the general-purpose registers
18 2.1.3 system registers the system registers are accessed by the lds and sts instructions. when an exception occurs, the contents of the pc are saved in the spc. the pc contents are also restored from the spc when ending exception processing with an rte instruction. the six system registers are: ? mach: multiply and accumulate high register ? macl: multiply and accumulate low register ? pr: procedure register ? pc: program counter ? fpul: fpu communication register ? fpscr: floating point status/control register figure 2.3 shows the system registers. 31 0 31 0 31 0 pc pr fpul* macl mach 31 0 fpscr* 31 0 system registers multiply and accumulate high and low registers (mach/l) store the results of multiply and multiply-and- accumulate operations. undefined after reset. floating point communication register (fpul) points the communication buffer between the cpu and the fpu. program counter (pc) indicates starting address of the current instruction incremented by four (two instructions). initialized to h'a000 0000 after reset. procedure register (pr) stores the return address for existing subroutines. undefined after reset. floating point status/control register (fpscr) stores status or controls information for floating point operations. note: * see section 3, floating point unit, for more information on the fpul and fpscr. figure 2.3 system register configuration
19 2.1.4 control registers the control registers can be accessed by the ldc and stc instructions in privileged mode. the gbr can also be accessed in user mode. the five control registers are: ? sr: status register ? ssr: saved status register ? spc: saved program counter ? gbr: global base register ? vbr: vector base register figure 2.4 shows the organization of the control registers.
20 ssr saved status register (ssr) stores current sr value at time of exception to indicate processor status in the return to instruction stream from exception handler. undefined after reset. saved program counter (spc) stores current pc value at time of exception to indicate return address at completion of exception processing. undefined after reset. global base register (gbr) stores the base address of the gbr-indirect addressing mode. the gbr-indirect addressing mode is used to transfer data to the register areas of the resident peripheral modules, and for logic operations. the gbr can be accessed in user mode. undefined after reset. vector base register (vbr) stores the base address of the exception processing vector area. initialized to h'00000000 after reset. 31 0 spc 31 0 gbr 31 0 vbr 31 0 md bl m 0 0 q i3 i2 i1 i0 0 0 s t status register (sr) 31 29 28 27 10 9 8 7 0 1 2 3 4 0rb 30 md: rb: bl: m and q bits: i3 i0: s bit: t bit: 0 bits: processor operation mode bit: indicates the processor operation mode as follows: 1 = privileged mode; 0 = user mode. becomes 1 when an exception or interrupt occurs. initialized to 1 reset. register bank bit: defines the general-purpose register used as bank in privileged mode. a logic 1 designates r0_bank1 r7_bank1 and r8 r15 are accessed as general purpose registers, and r0_bank0 r7_bank0 are only accessed by ldc and stc instructions; a logic zero designates r0_bank0 r7_bank0 and r8 r15 are accessed as general-purpose registers, and r0_bank1 r7_bank1 are only accessed by ldc and stc instructions. becomes 1 when an exception or interrupt occurs. initialized to 1 reset. block bit: masks exceptions and interrupts when 1. for details, see section 5, exception processing. when 0, accepts exceptions and interrupts. becomes 1 when an exception or interrupt occurs. initialized to 1 at reset. used by the divos/divou and div1 instructions. interrupt mask bits: a 4-bit field indicating the interrupt request mask level. the level of interrupt acceptance does not change when an interrupt occurs. initialized to b'1111 at reset. used by the mac instruction. the movt, cmp/cond, tas, tst, bt, bf, sett, clrt, and dt instructions use the t bit to indicate true (logic one) or false (logic zero). the addv/addc, subv/subc, divou/divos, div1, negc, shar/shal, shlr/shrl, rota/rotl, and rotcr/rotcl instructions also use the t bit to indicate a carry, borrow, overflow or underflow. always read as 0, and should always be written as 0. note: only the m, q, s, and t can be set or cleared by special instructions from user mode. undefined after reset. all other bits are read or written from privileged mode. figure 2.4 control registers configuration
21 2.2 data formats 2.2.1 data format in registers register operands are always longwords (32 bits). when the memory data operand size is only byte (8 bits) or word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 longword figure 2.5 longword operand 2.2.2 data format in memory memory data formats are classified into bytes, words, and longwords. memory can be accessed in bytes (8 bits), words (16 bits), or longwords (32 bits). memory operands that do not fill out 32 bits are sign-extended and stored in a register. access word operands from word boundaries (even addresses two bytes apart: 2n addresses) and longword operands from longword boundaries (even addresses four bytes apart: 4n addresses). other accesses cause address errors. byte operands can be accessed from any address. data formats can use either big endian or little endian byte order. use the external pin (md5) to set the endian at power-on reset. when md5 is low, the processor operates in big endian; when md5 is high, the processor operates in little endian. endians cannot be changed dynamically. numbers are always assigned to bit positions, from most significant to least significant and from left to right. for example, in a longword (32 bits), the leftmost bit (31) is the most significant and the rightmost bit (0) is the least significant. figure 2.6 shows the data format in memory. when little endian is used, data written in bytes (8 bits) should be read in bytes. data written in words (16 bits) should be read in words.
22 longword longword 31 0 31 0 31 0 15 23 7 byte0 byte1 byte2 byte3 word1 big endian word0 address a + 4 address a + 8 address a + 4 address a a + 1 a a + 2 a + 3 a + 11 a + 10 a + 9 a + 8 31 0 15 23 7 7 15 15 0 015150 0 0000 0 0 07 77 70 7 77 byte3 byte2 byte1 byte0 word0 little endian word1 address a address a + 8 figure 2.6 data formats in memory 2.3 instruction features 2.3.1 executing instructions data length : the sh7718r instruction set is implemented in fixed-length 16-bit wide instructions executed in a pipelined sequence with single-cycle execution for most instructions. all data is processed in 32-bit longword units. memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords. literals are sign-extended in arithmetic operations (mov, add, and cmp/eq instructions) and zero- extended in logical operations (tst, and, or, and xor instructions). load store architecture : the sh7718r features a load-store architecture in which basic operations are executed in registers. operations requiring memory access are executed in registers following register loading by data transfer instructions, except for bit-manipulation operations such as logical and functions, which are executed directly in memory. delayed branches : unconditional branching is implemented as delayed branch operations. pipeline disruptions due to branching are minimized by the execution of the instruction following the delayed branch instruction prior to branching. there are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. for example: bra trget add r1,r0 ;add is executed prior to branching to trget
23 t bits : the t bit in the status register (sr) is used to indicate the result of comparison operations, and is read as a true/false condition determining if a conditional branch is taken or not. to improve processing speed, the t bit logic state is modified only by specific instructions. an example of how the t bit may be used in a sequence of operations: add #1,r0 ;t bit not modified by add operation cmp/eq #0,r0 ;t bit set to 1 when r0 = 0 bt trget ;branch taken to trget when t bit = 1 (r0 = 0) literals : byte-wide literals are inserted directly into the instruction code as immediate data. to maintain the 16-bit fixed-length instruction code, word or longword literals are stored in a table in main memory rather than inserted directly into the instruction code. the memory table is accessed by the mov instruction using pc-relative addressing with displacement, as follows: mov.w @(disp,pc),r0 absolute addresses : as with word and longword literals, absolute addresses must also be stored in a table in main memory. the value of the absolute address is transferred to a register and the operand access is specified by indexed register-indirect addressing, with the absolute address loaded (as are word and longword immediate data) during instruction execution. 16-bit and 32-bit displacements : in the same way, 16-bit and 32-bit displacements used in referencing data also must be stored in a table in main memory. as with absolute addresses, the displacement value is transferred to a register and the operand access is specified by indexed register-indirect addressing, loading the displacement (as with word and longword immediate data) during instruction execution. 2.3.2 addressing modes table 2.2 describes addressing modes and effective address calculation.
24 table 2.2 addressing modes and effective addresses addressing mode instruction format effective address calculation equation direct register addressing rn the effective address is register rn. (the operand is the contents of register rn.) indirect register addressing @rn the effective address is the content of register rn. rn rn rn post-increment indirect register addressing @rn+ the effective address is the content of register rn. a constant is added to the content of rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. rn rn 1/2/4 + rn + 1/2/4 rn (after the instruction executes) byte: rn + 1 rn the effective address is the value obtained by subtracting a constant from rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. rn 1/2/4 rn 1/2/4 rn 1/2/4 byte: rn 1 2 4
25 table 2.2 addressing modes and effective addresses (cont) addressing mode instruction format effective address calculation equation indirect register addressing with displacement @(disp:4, rn) the effective address is rn plus a 4-bit displacement (disp). the value of disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. rn 1/2/4 +
26 table 2.2 addressing modes and effective addresses (cont) addressing mode instruction format effective address calculation equation indirect indexed gbr addressing @(r0, gbr) the effective address is the gbr value plus r0. gbr r0 gbr + r0 + gbr + r0 indirect pc addressing with displacement @(disp:8, pc) the effective address is the pc value plus an 8-bit displacement (disp). the value of disp is zero- extended, remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. for a longword operation, the lowest two bits of the pc value are masked. pc h'fffffffc + 2/4
27 table 2.2 addressing modes and effective addresses (cont) addressing mode instruction format effective address calculation equation pc relative addressing (cont) disp:12 the effective address is the pc value sign-extended with a 12-bit displacement (disp), doubled, and added to the pc value. pc 2 + #imm:8 the 8-bit immediate data (imm) for the mov, add, and cmp/eq instructions are sign-extended. #imm:8 the 8-bit immediate data (imm) for the trapa instruction is zero-extended and is quadrupled. note: in addressing modes that use the following displacements, the assembler statements of this manual show values before scaling (
28 2.3.3 instruction formats the instruction format table, table 2.3, describes the source operand and the destination operand. the meaning of the operand depends on the instruction code. the symbols used are as follows: ? xxxx: instruction code ? mmmm: source register ? nnnn: destination register ? iiii: immediate data ? dddd: displacement table 2.3 instruction formats instruction format source operand destination operand example 0 format xxxx xxxx xxxx xxxx 15 0 nop n format xxxx xxxx xxxx nnnn 15 0 nnnn: direct register movt rn control register or system register nnnn: direct register sts mach,rn control register or system register nnnn: indirect pre- decrement register stc.l sr,@?n m format xxxx mmmm xxxx xxxx 15 0 mmmm: direct register control register or system register ldc rm,sr mmmm: indirect post-increment register control register or system register ldc.l @rm+,sr mmmm: indirect register jmp @rn mmmm: pc relative using rn braf rm
29 table 2.3 instruction formats (cont) instruction format source operand destination operand example nm format mmmm: direct register nnnn: direct register add rm,rn nnnn xxxx xxxx 15 0 mmmm mmmm: direct register nnnn: indirect register mov.l rm,@rn mmmm: indirect post-increment register (multiply/ accumulate) nnnn: indirect post- increment register (multiply/ accumulate)* mach, macl mac.w @rm+,@rn+ mmmm: indirect post-increment register nnnn: direct register mov.l @rm+,rn mmmm: direct register nnnn: indirect pre- decrement register mov.l rm,@-rn mmmm: direct register nnnn: indirect indexed register mov.l rm,@(r0,rn) md format xxxx xxxx dddd 15 0 mmmm mmmmdddd: indirect register with displacement r0 (direct register) mov.b @(disp,rm),r0 nd4 format dddd nnnn xxxx 15 0 xxxx r0 (direct register) nnnndddd: indirect register with displacement mov.b r0,@(disp,rn) nmd format dddd dddd xxxx xxxx 15 0 mmmm: direct register nnnndddd: indirect register with displacement mov.l rm,@(disp,rn) mmmmdddd: indirect register with displacement nnnn: direct register mov.l @(disp,rm),rn
30 table 2.3 instruction formats (cont) instruction format source operand destination operand example d format dddd dddd dddd xxxx 15 0 dddddddd: indirect gbr with displacement r0 (direct register) mov.l @(disp,gbr),r0 r0(direct register) dddddddd: indirect gbr with displacement mov.l r0,@(disp,gbr) dddddddd: pc relative with displacement r0 (direct register) mova @(disp,pc),r0 dddddddd: pc relative bf label d12 format dddd dddd nnnn xxxx 15 0 dddddddddddd: pc relative bra label (label = disp + pc) nd8 format dddd dddd nnnn xxxx 15 0 dddddddd: pc relative with displacement nnnn: direct register mov.l @(disp,pc),rn i format iiiiiiii: immediate indirect indexed gbr and.b #imm,@(r0,gbr) i i i i i i i i xxxx xxxx 15 0 iiiiiiii: immediate r0 (direct register) and #imm,r0 iiiiiiii: immediate trapa #imm ni format nnnn i i i i i i i i xxxx 15 0 iiiiiiii: immediate nnnn: direct register add #imm,rn note: in multiply/accumulate instructions, nnnn is the source register.
31 2.4 instruction set 2.4.1 instruction set by classification table 2.4 summarizes instructions by functional class. table 2.4 classification of instructions classification types operation code function no. of instructions data transfer 5 mov data transfer immediate data transfer peripheral module data transfer structure data transfer 39 mova effective address transfer movt t bit transfer swap swap of upper and lower bytes xtrct extraction of the middle of registers connected arithmetic 21 add binary addition 33 operations addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division div0s initialization of signed division div0u initialization of unsigned division dmuls signed double-length multiplication dmulu unsigned double-length multiplication dt decrement and test exts sign extension extu zero extension mac multiply/accumulate, double-length multiply/accumulate operation
32 table 2.4 classification of instructions (cont) classification types operation code function no. of instructions arithmetic 21 mul double-length multiplication (32
33 table 2.4 classification of instructions (cont) classification types operation code function no. of instructions branch 9 bf conditional branch, conditional branch with delay (t = =
34 table 2.4 classification of instructions (cont) classification types operation code function no. of instructions floating point 16 fabs fp absolute value 23 fadd fp addition fcmp fp comparison fdiv fp division fldi0 fp load immediate zero fldi1 fp load immediate one flds fp load to fpul float fp convert from integer fmac fp multiply and accumulate fmov fp data transfer fmul fp multiply fneg fp negate fsqrt fp square root fsts fp store from fpul fsub fp subtract ftrc fp truncate and convert to integer total: 84 219 (211)* note: * the ldc and sts instructions include instructions for loading and storing to the fpu s control register. numbers in parentheses are with these subtracted. table 2.5 lists the instruction code format used in tables 2.6 through 2.13. these tables list various operation instructions.
35 table 2.5 instruction code format item format explanation instruction op.sz src,dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement operation ? s operand size) privilege indicates whether privileged mode applies cycles the execution cycles listed in the table are minimums. the actual number of cycles may be increased: 1. when contention occurs between instruction fetches and data access, or 2. when the destination register of the load instruction (memory : no change
36 table 2.6 data transfer instructions instruction operation code privi- lege cy- cles t bit mov #imm,rn #imm 1110nnnniiiiiiii 1 mov.w @(disp,pc),rn (disp 1001nnnndddddddd 1 mov.l @(disp,pc),rn (disp 1101nnnndddddddd 1 mov rm,rn rm 0110nnnnmmmm0011 1 mov.b rm,@rn rm 0010nnnnmmmm0000 1 mov.w rm,@rn rm 0010nnnnmmmm0001 1 mov.l rm,@rn rm 0010nnnnmmmm0010 1 mov.b @rm,rn (rm) 0110nnnnmmmm0000 1 mov.w @rm,rn (rm) 0110nnnnmmmm0001 1 mov.l @rm,rn (rm) 0110nnnnmmmm0010 1 mov.b rm,@?n rn 1 0010nnnnmmmm0100 1 mov.w rm,@?n rn 2 0010nnnnmmmm0101 1 mov.l rm,@?n rn 4 0010nnnnmmmm0110 1 mov.b @rm+,rn (rm) 0110nnnnmmmm0100 1 mov.w @rm+,rn (rm) 0110nnnnmmmm0101 1 mov.l @rm+,rn (rm) 0110nnnnmmmm0110 1 mov.b r0,@(disp,rn) r0 10000000nnnndddd 1 mov.w r0,@(disp,rn) r0 10000001nnnndddd 1 mov.l rm,@(disp,rn) rm 0001nnnnmmmmdddd 1 mov.b @(disp,rm),r0 (disp + rm) 10000100mmmmdddd 1 mov.w @(disp,rm),r0 (disp 10000101mmmmdddd 1 mov.l @(disp,rm),rn (disp 0101nnnnmmmmdddd 1 mov.b rm,@(r0,rn) rm 0000nnnnmmmm0100 1 mov.w rm,@(r0,rn) rm 0000nnnnmmmm0101 1
37 table 2.6 data transfer instructions (cont) instruction operation code privi- lege cy- cles t bit mov.l rm,@(r0,rn) rm 0000nnnnmmmm0110 1 mov.b @(r0,rm),rn (r0 + rm) 0000nnnnmmmm1100 1 mov.w @(r0,rm),rn (r0 + rm) 0000nnnnmmmm1101 1 mov.l @(r0,rm),rn (r0 + rm) 0000nnnnmmmm1110 1 mov.b r0,@(disp,gbr) r0 11000000dddddddd 1 mov.w r0,@(disp,gbr) r0 11000001dddddddd 1 mov.l r0,@(disp,gbr) r0 11000010dddddddd 1 mov.b @(disp,gbr),r0 (disp + gbr) 11000100dddddddd 1 mov.w @(disp,gbr),r0 (disp 11000101dddddddd 1 mov.l @(disp,gbr),r0 (disp 11000110dddddddd 1 mova @(disp,pc),r0 disp 11000111dddddddd 1 movt rn t 0000nnnn00101001 1 pref @rn (rn) 0000nnnn10000011 1 swap.b rm,rn rm 0110nnnnmmmm1000 1 swap.w rm,rn rm 0110nnnnmmmm1001 1 xtrct rm,rn rm: middle 32 bits of rn 0010nnnnmmmm1101 1
38 table 2.7 arithmetic instructions instruction operation code privi- lege cycles t bit add rm,rn rn + rm 0011nnnnmmmm1100 1 add #imm,rn rn + imm 0111nnnniiiiiiii 1 addc rm,rn rn + rm + t 0011nnnnmmmm1110 1 carry addv rm,rn rn + rm 0011nnnnmmmm1111 1 overflow cmp/eq #imm,r0 if r0 = 10001000iiiiiiii 1 comparison result cmp/eq rm,rn if rn = 0011nnnnmmmm0000 1 comparison result cmp/hs rm,rn if rn 0011nnnnmmmm0010 1 comparison result cmp/ge rm,rn if rn 0011nnnnmmmm0011 1 comparison result cmp/hi rm,rn if rn > rm with unsigned data, 1 0011nnnnmmmm0110 1 comparison result cmp/gt rm,rn if rn > rm with signed data, 1 0011nnnnmmmm0111 1 comparison result cmp/pz rn if rn 0100nnnn00010001 1 comparison result cmp/pl rn if rn > 0, 1 0100nnnn00010101 1 comparison result cmp/str rm,rn if rn and rm have an equivalent byte, 1 0010nnnnmmmm1100 1 comparison result div1 rm,rn single-step division (rn/rm) 0011nnnnmmmm0100 1 calculation result div0s rm,rn msb of rn 0010nnnnmmmm0111 1 calculation result div0u 0 0000000000011001 10
39 table 2.7 arithmetic instructions (cont) instruction operation code privi- lege cycles t bit dmuls.l rm,rn signed operation of rn 0011nnnnmmmm1101 2 5* 1 dmulu.l rm,rn unsigned operation of rn 0011nnnnmmmm0101 2 5* 1 dt rn rn 1 = 0100nnnn00010000 1 comp-arison result exts.b rm,rn a byte in rm is sign- extended 0110nnnnmmmm1110 1 exts.w rm,rn a word in rm is sign- extended 0110nnnnmmmm1111 1 extu.b rm,rn a byte in rm is zero- extended 0110nnnnmmmm1100 1 extu.w rm,rn a word in rm is zero- extended 0110nnnnmmmm1101 1 mac.l @rm+,@rn+ signed operation of (rn) + 0000nnnnmmmm1111 2 5* 1 mac.w @rm+,@rn+ signed operation of (rn) + 0100nnnnmmmm1111 2 5* 1 mul.l rm,rn rn 0000nnnnmmmm0111 2 5* 1 muls.w rm,rn signed operation of rn 0010nnnnmmmm1111 1 3* 2 mulu.w rm,rn unsigned operation of rn 0010nnnnmmmm1110 1 3* 2
40 table 2.7 arithmetic instructions (cont) instruction operation code privi- lege cycles t bit neg rm,rn 0 rm 0110nnnnmmmm1011 1 negc rm,rn 0 rm t 0110nnnnmmmm1010 1 borrow sub rm,rn rn rm 0011nnnnmmmm1000 1 subc rm,rn rn rm t 0011nnnnmmmm1010 1 borrow subv rm,rn rn rm 0011nnnnmmmm1011 1 underflow notes: 1. the normal minimum number of execution cycles is 2, but 5 cycles are required when the results of an operation are read from the mac register immediately after the instruction. 2. the normal minimum number of execution cycles is 1, but 3 cycles are required when the results of an operation are read from the mac register immediately after a mul instruction.
41 table 2.8 logic operation instructions instruction operation code privi- lege cy- cles t bit and rm,rn rn & rm 0010nnnnmmmm1001 1 and #imm,r0 r0 & imm 11001001iiiiiiii 1 and.b #imm,@(r0,gbr) (r0 + gbr) & imm 11001101iiiiiiii 3 not rm,rn ~rm 0110nnnnmmmm0111 1 or rm,rn rn | rm 0010nnnnmmmm1011 1 or #imm,r0 r0 | imm 11001011iiiiiiii 1 or.b #imm,@(r0,gbr) (r0 + gbr) | imm 11001111iiiiiiii 3 tas.b @rn if (rn) is 0, 1 0100nnnn00011011 3 test result tst rm,rn rn & rm; if the result is 0, 1 0010nnnnmmmm1000 1 test result tst #imm,r0 r0 & imm; if the result is 0, 1 11001000iiiiiiii 1 test result tst.b #imm,@(r0,gbr) (r0 + gbr) & imm; if the result is 0, 1 11001100iiiiiiii 3 test result xor rm,rn rn ^ rm 0010nnnnmmmm1010 1 xor #imm,r0 r0 ^ imm 11001010iiiiiiii 1 xor.b #imm,@(r0,gbr) (r0 + gbr) ^ imm 11001110iiiiiiii 3
42 itable 2.9 shift instructions instruction operation code privi- lege cy- cles t bit rotl rn t 0100nnnn00000100 1 msb rotr rn lsb 0100nnnn00000101 1 lsb rotcl rn t 0100nnnn00100100 1 msb rotcr rn t 0100nnnn00100101 1 lsb shad rm,rn rn 0100nnnnmmmm1100 1 shal rn t 0100nnnn00100000 1 msb shar rn msb 0100nnnn00100001 1 lsb shld rm,rn rn 0100nnnnmmmm1101 1 shll rn t 0100nnnn00000000 1 msb shlr rn 0 0100nnnn00000001 1 lsb shll2 rn rn << 2 0100nnnn00001000 1 shlr2 rn rn >> 2 0100nnnn00001001 1 shll8 rn rn << 8 0100nnnn00011000 1 shlr8 rn rn >> 8 0100nnnn00011001 1 shll16 rn rn << 16 0100nnnn00101000 1 shlr16 rn rn >> 16 0100nnnn00101001 1
43 table 2.10 branch instructions instruction operation code privi- lege cy- cles t bit bf label if t = = 10001011dddddddd 3/1* bf/s label delayed branch, if t = = 10001111dddddddd 2/1* bt label delayed branch, if t = = 10001001dddddddd 3/1* bt/s label if t = = 10001101dddddddd 2/1* bra label delayed branch, disp 1010dddddddddddd 2 braf rm rm + pc 0000mmmm00100011 2 bsr label delayed branch, pc 1011dddddddddddd 2 bsrf rm pc 0000mmmmm00000011 2 jmp @rm delayed branch, rm 0100mmmm00101011 2 jsr @rm delayed branch, pc 0100mmmm00001011 2 rts delayed branch, pr 0000000000001011 2 note: * one state when it does not branch.
44 table 2.11 system control instructions instruction operation code privi- lege cy- cles t bit clrmac 0 0000000000101000 1 clrs 0 0000000001001000 1 clrt 0 0000000000001000 10 ldc rm,sr rm 0100mmmm00001110 yes 5 lsb ldc rm,gbr rm 0100mmmm00011110 1 ldc rm,vbr rm 0100mmmm00101110 yes 1 ldc rm,ssr rm 0100mmmm00111110 yes 1 ldc rm,spc rm 0100mmmm01001110 yes 1 ldc rm,r0_bank rm 0100mmmm10001110 yes 1 ldc rm,r1_bank rm 0100mmmm10011110 yes 1 ldc rm,r2_bank rm 0100mmmm10101110 yes 1 ldc rm,r3_bank rm 0100mmmm10111110 yes 1 ldc rm,r4_bank rm 0100mmmm11001110 yes 1 ldc rm,r5_bank rm 0100mmmm11011110 yes 1 ldc rm,r6_bank rm 0100mmmm11101110 yes 1 ldc rm,r7_bank rm 0100mmmm11111110 yes 1 ldc.l @rm+,sr (rm) 0100mmmm00000111 yes 7 lsb ldc.l @rm+,gbr (rm) 0100mmmm00010111 1 ldc.l @rm+,vbr (rm) 0100mmmm00100111 yes 1 ldc.l @rm+,ssr (rm) 0100mmmm00110111 yes 1 ldc.l @rm+,spc (rm) 0100mmmm01000111 yes 1 ldc.l @rm+, r0_bank (rm) 0100mmmm10000111 yes 1 ldc.l @rm+, r1_bank (rm) 0100mmmm10010111 yes 1 ldc.l @rm+, r2_bank (rm) 0100mmmm10100111 yes 1 ldc.l @rm+, r3_bank (rm) 0100mmmm10110111 yes 1
45 table 2.11 system control instructions (cont) instruction operation code privi- lege cy- cles t bit ldc.l @rm+, r4_bank (rm) 0100mmmm11000111 yes 1 ldc.l @rm+, r5_bank (rm) 0100mmmm11010111 yes 1 ldc.l @rm+, r6_bank (rm) 0100mmmm11100111 yes 1 ldc.l @rm+, r7_bank (rm) 0100mmmm11110111 yes 1 lds rm,mach rm 0100mmmm00001010 1 lds rm,macl rm 0100mmmm00011010 1 lds rm,pr rm 0100mmmm00101010 1 lds.l @rm+,mach (rm) 0100mmmm00000110 1 lds.l @rm+,macl (rm) 0100mmmm00010110 1 lds.l @rm+,pr (rm) 0100mmmm00100110 1 ldtlb pteh/ptel 0000000000111000 yes 1 nop no operation 0000000000001001 1 pref @rm (rm) 0000mmmm10000011 1 rte delayed branch, ssr/spc 0000000000101011 yes 4 sets 1 0000000001011000 1 sett 1 0000000000011000 11 sleep sleep 0000000000011011 yes 4* 1 stc sr,rn sr 0000nnnn00000010 yes 1 stc gbr,rn gbr 0000nnnn00010010 1 stc vbr,rn vbr 0000nnnn00100010 yes 1 stc ssr,rn ssr 0000nnnn00110010 yes 1 stc spc,rn spc 0000nnnn01000010 yes 1 stc r0_bank,rn r0_bank 0000nnnn10000010 yes 1 stc r1_bank,rn r1_bank 0000nnnn10010010 yes 1 stc r2_bank,rn r2_bank 0000nnnn10100010 yes 1 stc r3_bank,rn r3_bank 0000nnnn10110010 yes 1 stc r4_bank,rn r4_bank 0000nnnn11000010 yes 1
46 table 2.11 system control instructions (cont) instruction operation code privi- lege cy- cles t bit stc r5_bank,rn r5_bank 0000nnnn11010010 yes 1 stc r6_bank,rn r6_bank 0000nnnn11100010 yes 1 stc r7_bank,rn r7_bank 0000nnnn11110010 yes 1 stc.l sr,@?n rn 4 0100nnnn00000011 yes 1 stc.l gbr,@?n rn 4 0100nnnn00010011 1 stc.l vbr,@?n rn 4 0100nnnn00100011 yes 1 stc.l ssr,@?n rn 4 0100nnnn00110011 yes 1 stc.l spc,@?n rn 4 0100nnnn01000011 yes 1 stc.l r0_bank, @?n rn 4 0100nnnn10000011 yes 2 stc.l r1_bank, @?n rn 4 0100nnnn10010011 yes 2 stc.l r2_bank, @?n rn 4 0100nnnn10100011 yes 2 stc.l r3_bank, @?n rn 4 0100nnnn10110011 yes 2 stc.l r4_bank, @?n rn 4 0100nnnn11000011 yes 2 stc.l r5_bank, @?n rn 4 0100nnnn11010011 yes 2 stc.l r6_bank, @?n rn 4 0100nnnn11100011 yes 2 stc.l r7_bank, @?n rn 4 0100nnnn11110011 yes 2 sts mach,rn mach 0000nnnn00001010 1 sts macl,rn macl 0000nnnn00011010 1
47 table 2.11 system control instructions (cont) instruction operation code privi- lege cy- cles t bit sts pr,rn pr 0000nnnn00101010 1 sts.l mach,@?n rn 4 0100nnnn00000010 1 sts.l macl,@?n rn 4 0100nnnn00010010 1 sts.l pr,@?n rn 4 0100nnnn00100010 1 trapa #imm pc/sr 11000011iiiiiiii 6 notes: 1. the number of execution states before the chip enters the sleep state. 2. this table lists the minimum execution cycles. in practice, the number of execution cycles increases when the instruction fetch is in contention with data access or when the destination register of a load instruction (memory
48 table 2.12 floating point instructions instruction operation code privi- lege cy- cles t bit fabs frn |frn| 1111nnnn01011101 1 fadd frm,frn frn + frm 1111nnnnmmmm0000 1 fcmp/eq frm, frn (frn = frm) 1 1111nnnnmmmm0100 1 comparison result fcmp/gt frm, frn (frn> frm) 1 1111nnnnmmmm0101 1 comparison result fdiv frm, frn frn/frm 1111nnnnmmmm0011 13 fldi0 frn 0x00000000 1111nnnn10001101 1 fldi1 frn 0x3f800000 1111nnnn10011101 1 flds frm, fpul frm 1111nnnn00011101 1 float fpul, frn (float)fpul 1111nnnn00101101 1 fmac fr0, frm, frn fr0 1111nnnnmmmm1110 1 fmov frm, frn frm 1111nnnnmmmm1100 1 fmov.s @(r0,rm), frn (r0 + rm) 1111nnnnmmmm0110 1 fmov.s @rm+, frn (rm) 1111nnnnmmmm1001 1 fmov.s @rm, frn (rm) 1111nnnnmmmm1000 1 fmov.s frm, @(r0, rn) frm 1111nnnnmmmm0111 1 fmov.s frm, @-rn rn 4 1111nnnnmmmm1011 1 fmov.s frm, @rn frm 1111nnnnmmmm1010 1 fmul frm, frn frn 1111nnnnmmmm0010 1 fneg frn frn 1111nnnn01001101 1 fsqrt frn 1111nnnn01101101 13 fsts fpul, frn fpul 1111nnnn00001101 1 fsub frm, frn frn frm 1111nnnnmmmm0001 1 ftrc frm, fpul (long) frm 1111nnnn00111101 1
49 table 2.13 cpu instructions related to fpu instruction operation code privi- lege cy- cles t bit lds rm, fpscr rm 0100nnnn01101010 1 lds rm, fpul rm 0100nnnn01011010 1 lds.l @rm+, fpscr @rm 0100nnnn01100110 1 lds.l @rm+, fpul @rm 0100nnnn01010110 1 sts fpscr, rn fpscr 0000nnnn01101010 1 sts fpul, rn fpul 0000nnnn01011010 1 sts.l fpscr, @-rn rn 4, fpscr 0100nnnn01100010 1 sts.l fpul, @-rn rn 4, fpul 0100nnnn01010010 1
50 2.4.2 operation code map table 2.14 is an operation code map. table 2.14 operation code map instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011?111 msb lsb md: 00 md: 01 md: 10 md: 11 0000 rn fx 0000 0000 rn fx 0001 0000 rn 00md 0010 stc sr,rn stc gbr,rn stc vbr,rn stc ssr,rn 0000 rn 01md 0010 stc spc,rn 0000 rn 10md 0010 stc r0_bank,rn stc r1_bank,rn stc r2_bank,rn stc r3_bank,rn 0000 rn 11md 0010 stc r4_bank,rn stc r5_bank,rn stc r6_bank,rn stc r7_bank,rn 0000 rn 00md 0011 bsrf rm braf rm 0000 rm 10md 0011 pref @rm 0000 rn rm 01md mov.b rm, @(r0,rn) mov.w rm, @(r0,rn) mov.l rm, @(r0,rn) mul.l rm,rn 0000 0000 00md 1000 clrt sett clrmac ldtlb 0000 0000 01md 1000 clrs sets 0000 0000 fx 1001 nop divou 0000 0000 fx 1010 0000 0000 fx 1011 rts sleep rte 0000 rn fx 1000 0000 rn fx 1001 movt rn 0000 rn 00md 1010 sts mach,rn sts macl,rn sts pr,rn 0000 rn 01md 1010 sts fpul,rn sts fpscr,rn 0000 rn fx 1011 0000 rn rm 11md mov.b @(r0,rm),rn mov.w @(r0,rm),rn mov.l @(r0,rm),rn mac.l @rm+,@rn+ 0001 rn rm disp mov.l rm,@(disp:4,rn) 0010 rn rm 00md mov.b rm,@rn mov.w rm,@rn mov.l rm,@rn 0010 rn rm 01md mov.b rm,@-rn mov.w rm,@?n mov.l rm,@?n div0s rm,rn 0010 rn rm 10md tst rm,rn and rm,rn xor rm,rn or rm,rn 0010 rn rm 11md cmp/str rm,rn xtrct rm,rn mulu.w rm,rn muls.w rm,rn 0011 rn rm 00md cmp/eq rm,rn cmp/hs rm,rn cmp/ge rm,rn
51 table 2.14 operation code map (cont) instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011?111 msb lsb md: 00 md: 01 md: 10 md: 11 0011 rn rm 01md div1 rm,rn dmulu.l rm,rn cmp/hi rm,rn cmp/gt rm,rn 0011 rn rm 10md sub rm,rn subc rm,rn subv rm,rn 0011 rn rm 11md add rm,rn dmulu.l rm,rn addc rm,rn addv rm,rn 0100 rn fx 0000 shll rn dt rn shal rn 0100 rn fx 0001 shlr rn cmp/pz rn shar rn 0100 rn 00md 0010 sts.l mach, @?n sts.l macl, @?n sts.l pr, @?n 0100 rn 01md 0010 sts.l fpul, @?n sts.l fpscr, @?n 0100 rn 00md 0011 stc.l sr,@?n stc.l gbr,@?n stc.l vbr,@?n stc.l ssr,a-rn 0100 rn 01md 0011 stc.l spc,@-rn 0100 rn 10md 0011 stc.l r0_bank,@-rn stc.l r1_bank,@-rn stc.l r2_bank,@-rn stc.l r3_bank,@-rn 0100 rn 11md 0011 stc.l r4_bank,@-rn stc.l r5_bank,@-rn stc.l r6_bank,@-rn stc.l r7_bank,@-rn 0100 rn fx 0100 rotl rn rotcl rn 0100 rn fx 0101 rotr rn cmp/pl rn rotcr rn 0100 rm 00md 0110 lds.l @rm+,mach lds.l @rm+,macl lds.l @rm+,pr 0100 rm 01md 0110 lds.l @rm+,fpul lds.l @rm+,fpscr 0100 rm 00md 0111 ldc.l @rm+,sr ldc.l @rm+,gbr ldc.l @rm+,vbr ldc.l @rm+,ssr 0100 rm 01md 0111 ldc.l @rm+,spc 0100 rm 10md 0111 ldc.l @rm+,r0_bank ldc.l @rm+,r1_bank ldc.l @rm+,r2_bank ldc.l @rm+,r3_bank 0100 rm 11md 0111 ldc.l @rm+,r4_bank ldc.l @rm+,r5_bank ldc.l @rm+,r6_bank ldc.l @rm+,r7_bank 0100 rn fx 1000 shll2 rn shll8 rn shll16 rn 0100 rn fx 1001 shlr2 rn shlr8 rn shlr16 rn 0100 rm 00md 1010 lds rm,mach lds rm,macl lds rm,pr 0100 rm 01md 1010 lds rm,fpul lds rm,fpscr
52 table 2.14 operation code map (cont) instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011?111 msb lsb md: 00 md: 01 md: 10 md: 11 0100 rn fx 1011 jsr @rm tas.b @rn jmp @rm 0100 rm rm 1100 shad rm,rn 0100 rm rm 1101 shld rm,rn 0100 rm 00md 1110 ldc rm,sr ldc rm,gbr ldc rm,vbr ldc rm,ssr 0100 rm 01md 1110 ldc rm,spc 0100 rm 10md 1110 ldc rm,r0_bank ldc rm,r1_bank ldc rm,r2_bank ldc rm,r3_bank 0100 rm 11md 1110 ldc rm,r4_bank ldc rm,r5_bank ldc rm,r6_bank ldc rm,r7_bank 0100 rn rm 1111 mac.w @rm+,@rn+ 0101 rn rm disp mov.l @(disp:4,rm),rn 0110 rn rm 00md mov.b @rm,rn mov.w @rm,rn mov.l @rm,rn mov rm,rn 0110 rn rm 01md mov.b @rm+,rn mov.w @rm+,rn mov.l @rm+,rn not rm,rn 0110 rn rm 10md swap.b rm,rn swap.w rm,rn negc rm,rn neg rm,rn 0110 rn rm 11md extu.b rm,rn extu.w rm,rn exts.b rm,rn exts.w rm,rn 0111 rn imm add #imm:8,rn 1000 00md rn disp mov.b r0, @(disp:4,rn) mov.w r0, @(disp:4,rn) 1000 01md rm disp mov.b @(disp:4, rm),r0 mov.w @(disp:4, rm),r0 1000 10md imm/disp cmp/eq #imm:8,r0 bt disp:8 bf label:8 1000 10md imm/disp bt/s disp:8 bf/s label:8 1001 rn disp mov.w @(disp:8,pc),rn 1010 disp bra label:12 1011 disp bsr label:12 1100 00md imm/disp mov.b r0, @(disp:8, gbr) mov.w r0, @(disp:8, gbr) mov.l r0, @(disp:8, gbr) trapa #imm:8 1100 01md disp mov.b @(disp:8, gbr),r0 mov.w @(disp:8, gbr),r0 mov.l @(disp:8, gbr),r0 mova @(disp:8, pc),r0
53 table 2.14 operation code map (cont) instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011?111 msb lsb md: 00 md: 01 md: 10 md: 11 1100 10md imm tst #imm:8,r0 and #imm:8,r0 xor #imm:8,r0 or #imm:8,r0 1100 11md imm tst.b #imm:8, @(r0,gbr) and.b #imm:8, @(r0,gbr) xor.b #imm:8, @(r0,gbr) or.b #imm:8, @(r0,gbr) 1101 rn disp mov.l @(disp:8,pc),rn 1110 rn imm mov #imm:8,rn 1111 rn rm 00md fadd frm,frn fsub frm,frn fmul frm,frn fdiv frm,frn 1111 rn rm 01md fcmp/eq frm,frn fcmp/gt frm,frn fmov.s @(r0,rm),frm fmov.s frm,@(r0,rn) 1111 rn rm 10md fmov.s @rm,frn fmov.s @rm+,frm fmov.s frm,@rn fmov.s frm,@- rn 1111 rn rm 1100 fmov frm,frn 1111 rn 00md 1101 fsts fpul,frn flds frn,fpul float fpul,frn ftrc frn, fpul 1111 rn 01md 1101 fneg frn fabs frn fsqrt frn 1111 rn 10md 1101 fldi0 frn fldi1 frn 1111 rn rm 1110 fmac fr0,frm,frn note: further details are also given in the sh-3/sh-3e programming manual. 2.5 processing states and processing modes 2.5.1 processing states the cpu has five processing states: reset, exception processing, bus release, program execution, and power-down. reset state: the cpu resets in the reset state. this occurs when the reset pin level goes low. when the breq pin is high, the result is a power-on reset; when it is low, a manual reset will occur. see section 5, exception processing, for more information on resets. a power-on reset initializes the cpu? internal states and on-chip peripheral module registers. a manual reset initializes the cpu? internal states and all on-chip peripheral modules except the bus state controller (bsc). the bsc is not initialized during a manual reset, so refresh operations continue. for more information, see the register descriptions in their individual sections.
54 exception processing state : the exception processing state is a transient state that occurs when exception processing sources such as resets, ordinary exceptions, or interrupts alter the cpu? processing state flow. for a reset, the cpu branches to h'a0000000 and starts running the user-created exception processing program. for an ordinary exception or interrupt, the program counter (pc) is saved to the saved program counter (spc) and the status register (sr) is saved to the saved status register (ssr). the cpu branches to the start address of the user-created exception service routine found by adding the data in the vector base register to the vector offset and the program starts running. see section 5, exception processing, for more information on ordinary exceptions, interrupts, and resets. program execution state : in the program execution state, the cpu sequentially executes the program. power-down state : in the power-down state, the cpu operation halts and power consumption declines. the sleep instruction places the cpu in the power-down state. this state has two modes: sleep mode and standby mode. see section 9, power-down mode, for more information on the power-down mode. bus release state : in the bus release state, the cpu releases access rights to the bus to the device that has requested them. figure 2.7 shows the transitions between the states.
55 from any state except hardware standby mode when reset breq reset breq reset breq reset breq reset breq reset breq there are two processing modes: privileged mode and user mode. use the processing mode bit (md) in the status register (sr) to select the mode. when md is 1, the mode is privileged; when md is 0, the mode is user. md is always 1 in the reset and exception states. when exception processing ends, the md bit is cleared to switch to user mode. some bits and registers can only be accessed in privileged mode.
56 2.6 usage note operations may not be performed correctly when the following sequences are executed with the cache on. address instruction 4n mac.l (or mac.w, dmuls.l, dmulu.l, mul.l) 4n+2 mac.l (or mac.w, dmuls.l, dmulu.l, mul.l) 4n+4 sts(.l)/lds(.l) mach/macl or 4n+2 mac.l (or mac.w, dmuls.l, dmulu.l, mul.l) 4n+4 nop (or one-cycle instruction except mac.w instruction* 1 or branch instruction* 2 ) 4n+6 mac.l (or mac.w, dmuls.l, dmulu.l, mul.l) 4n+8 sts(.l)/lds(.l) mach/macl notes: 1. muls.w, mulu.w, mac.l, mac.w, dmuls.l, dmulu.l, mul.l, muls.w, mulu.w 2. bf, bf/s, bt, bt/s, bra, braf, bsr, bsrf, jmp, jsr, rts software remedy: this problem can be avoided in either of the following ways. 1. do not use the above sequences. 2. when performing sts/lds on the macl/mach register after consecutive execution of mac instructions, insert an nop instruction between the mac instructions and sts/lds instruction.
57 section 3 floating point unit 3.1 introduction the sh7718r has a built-in floating point operations unit (fpu). figure 3.1 shows the fpu registers. fr0 fr1 fr2 fr3 fr4 fr5 fr6 fr7 fr8 fr9 fr10 fr11 fr12 fr13 fr14 fr15 31 0 fpul* 31 0 fpscr* 31 0 floating point registers system registers fr0 functions as the index register for fmac instructions. floating point communication register (fpul) indicates the buffer as the communication register between the cpu and the fpu. floating point status/control register (fpscr) stores status or control information for floating point operations. note: * see section 3.3, floating point registers and fpu systems registers, for more information. figure 3.1 register set overview: floating point and system registers
58 3.2 floating point registers and system registers for fpu 3.2.1 floating point register file the sh7718r provides sixteen 32-bit single-precision floating point registers. register designators are always 4-bits. in assembly language, the floating point registers are designated as fr0, fr1, fr2, etc. fr0 functions as the index for fmac instructions. 3.2.2 floating point communication register (fpul) information is transferred between the fpu and the cpu through a communication register, fpul, which is analogous to the macl and mach registers of the integer unit. the sh7718r provides this communication register because of the differences between integer format and fpu format. fpul is a 32-bit system register, accessed on the cpu side by lds and sts instructions. 3.2.3 floating point status/control register (fpscr) the sh7718r implements a floating point status and control register, fpscr, as a system register accessed through the lds and sts instructions (figure 3.2). fpscr is available for modification by user programs. the fpscr is part of the process context. it must be saved across context switches and may need to be saved across procedure calls. the fpscr is a 32-bit register that controls fpu rounding, handling of denormalized values, and captures details about floating point exceptions. in the sh7718r, only the following modes are supported for these functions. ? rounding mode: rounding toward 0. ? handling of denormalized values: when denormalized values are in the source or destination operand, they are always treated as 0. ? fpu exceptions: divide by zero (z) and invalid (v).
59 0 -------------------- 0 1 cv cz 0 0 0 ev ez 0 0 0 fv fz 0 0 0 cause enable flag 0 1 0 31 18 19 17 16 15 12 11 10 14 7 96 2 4 510 cv: invalid-operation cause bit 1: invalid-operation exception occurred during execution of the current instruction 0: invalid-operation exception did not occur cz: divide-by-zero cause bit 1: divide-by-zero exception occurred during the execution of the current instruction 0: divide-by-zero exception did not occur ev: invalid-operation exception enable bit 1: enable invalid-operation exception 0: disable invalid-operation exception and return qnan as a result ez: divide-by-zero exception enable bit 1: enable divide-by-zero exception 0: disable divide-by-zero exception and return correctly signed infinity fv: invalid-operation exception flag bit 1: invalid-operation exception occurred during execution of the current instruction 0: invalid-operation exception did not occur fz: divide-by-zero exception flag bit 1: divide-by-zero exception occurred during the execution of the current instruction 0: divide-by-zero exception did not occur note: with the exception of the above bits, all bits are reserved as shown in the figures and cannot be modified even by lds instruction. figure 3.2 floating point status/control register the bits in the cause field indicate the cause of exception for the executing of the current instruction. the cause bits are modified by execution of a floating point instruction. these bits are set to 0 or 1, depending on occurrence or non-occurrence of exception conditions during the execution of a single instruction. the bits in the enable field indicate the specific types of exceptions that are enabled to cause an exception, that is, change of flow to an exception handling procedure. an exception occurs if the enable bit and the corresponding cause bit are set by the execution of the current instruction. the bits in the flag field are used to capture the cumulative effect of all exceptions during the execution of a sequence of instructions. these bits, once set by an instruction, can not be reset by following instructions. the bits in this field can only be reset by an explicit store operation on fpscr. see section 3.4, floating point exceptions model, for more information on handling of floating point exceptions.
60 3.3 floating point format 3.3.1 floating point format the sh7718r supports single-precision floating point operations. it also conforms fully to the ieee754 standard. floating point numbers are composed of three fields: ? sign field : s ? exponent field : e ? mantissa field : f the exponent is biased. in other words: e = e + bias the range of unbiased exponents e is e min ? to e max +1. the two values (e min ? and e max +1) are distinguished as follows. e min ? represents zero (sign is both positive and negative) and a denormalized number while e max +1 represents positive and negative infinity and a not-a-number (nan). in single-precision operations, the bias value is 127, e min is ?26, and e max is 127. 31 30 23 22 0 se f figure 3.3 floating point format the value v of the floating point number is determined as follows: if e== e max +1 and f!=0, then v is not a number (nan) regardless of sign s if e== e max +1 and f==0, then v=(?) s (infinity) [positive or negative infinity] if e min <=e<= e max , then v =(?) s 2 e (1.f) [normalized number] if e== e min ? and f!=0, then v =(?) s 2 emin (0.f) [denormalized number] if e== e min ? and f==0, then v =(?) s 0 [positive or negative zero] 3.3.2 not a number (nan) in not-a-number (nan) expressions in single-precision operations, at least one of the bits 22? is set. set bit 22 for a signaling nan (snan). when bit 22 is reset, the value is then the quiet nan (qnan).
61 the following figure shows the bit pattern of the not-a-number (nan). bit n in the figure is set for snan and reset for qnan. an x indicates a don?-care bit. at least one of bits 22-0 must be set. in a not-a-number (nan), the sign bit is a don?-care bit. 31 30 23 22 0 x 11111111 nxxxxxxxxxxxxxxxxxxxxxx n = 1: snan n = 0: qnan figure 3.4 nan bit pattern when a not-a-number (snan) is entered in the operation that generates the floating point value: ? when the ev bit is reset in the fpscr, the operation result (output) is qnan. ? when the ev bit is set in the fpscr, an invalid operation exception occurs. in such cases, the contents of the register at the destination side of the operation do not change. when qnan is input to the operation that generates the floating point value and snan is not input to the operation, the output will always be qnan regardless of how the ev bit is set in the fpscr. no exception will occur. see the sh-3, sh-3e programming manual for more information on floating point operations when a not-a-number (nan) is input. 3.3.3 denormalized values denormalized floating point values are expressed by a biased exponent of 0, a nonzero mantissa, and a hidden bit of 0. in the sh7718r? floating point unit, denormalized values (operand source or operation result) are uniformly flushed with 0 in floating point operations (other than copy) that generate values. 3.3.4 other special values other special values are as stipulated by standard ieee754. table 3.1 shows the seven different types of special values in floating point value expressions.
62 table 3.1 special value expressions in single-precision stipulated in ieee754 value expression +0.0 0x00000000 -0.0 0x80000000 denormalized number see section 3.3.3, denormalized values +inf 0x7f800000 inf 0xff800000 qnan (quiet nan) see section 3.3.2, not a number (nan) snan (signaling nan) see section 3.3.2, not a number (nan) 3.4 floating point exception model 3.4.1 enabled exception invalid-operation and divide-by-zero exceptions are enabled by setting the enable bit for the relevant exception (the ev or ez bit) in fpscr. all exceptions caused by the fpu are mapped as fpu exception events. the meaning of an individual exception is determined by software by reading the fpscr system register and analyzing the information held there. 3.4.2 disabled exception if enable bit ev is not set in fpscr, the result of an invalid operation will be qnan (with the exception of fcmp and ftrc). if enable bit ez is not set, division by zero will return infinity with the sign of the current expression (+ or -). the other floating-point exceptions specified in the ieee754 standard?nexact, overflow, and underflow?re not supported by the sh7718r. in these cases, the sh7718r operates as described below. ? an overflow will produce the number whose absolute value is the largest representable finite number in the format with the correct sign bit. an underflow will produce a correctly signed zero. if the result of an operation is inexact, the destination register will hold the inexact result. 3.4.3 exception event and code for fpu all fpu exceptions are mapped onto the single general exception event at address h'0x120. loads and stores of system registers fpul and fpscr cause the normal memory management general exceptions.
63 3.4.4 alignment of floating point data in memory single precision floating point data is aligned on modulus-4 boundaries, that is, in the same fashion as sh7718r long integers. 3.4.5 arithmetic with special operands all arithmetic with special operands (qnan, snan, +inf, ?nf, +0, ?) follows ieee754 rules. see the sh-3, sh-3e programming manual for details. 3.5 synchronization issues synchronization with cpu: floating-point and cpu instructions are issued serially in program order, but may complete out-of-order due to execution cycle differences. a floating point operation that accesses only fpu resources does not require synchronization with the cpu, and subsequent cpu operations can complete before the completion of the floating point operation. therefore an optimized program can hide the execution cycle of a long-execution-cycle floating point operation such as divide. a floating point operation such as compare that accesses cpu resources, however, requires synchronization to ensure program order. floating point instructions requiring synchronization: loads, stores, compares/tests, and instructions accessing fpul access cpu resources and therefore require synchronization. loads and stores refer to general registers. post-increment loads and pre-decrement stores modify general registers. compares/tests modify the t bit. instructions accessing fpul refer to or modify fpul. these references and modifications must be synchronized with the cpu. maintaining program order on exceptions: floating point instructions are never completed until subsequent cpu instructions are completed. if an fpu exception is detected before subsequent cpu instructions finish and an fpu exception occurs, subsequent cpu instructions are canceled. during a floating point instruction execution, if a subsequent instruction causes an exception, the floating point instruction is left executing and fpu resources cannot be accessed by other instructions. the other instructions must await the completion of the floating point operation before they can access. this ensures program order.
65 section 4 memory management unit (mmu) 4.1 overview 4.1.1 features the sh7718r has an on-chip memory management unit (mmu) that implements address translation and features a resident translation look-aside buffer (tlb) that caches information for user-created address translation tables located in external memory. it enables high-speed translation of virtual addresses into physical addresses. address translation uses the paging system and supports two page sizes (1 kbyte and 4 kbytes). it defines permitted access types to logical address space for privileged and user modes to support memory protection. 4.1.2 function the mmu is devised to enable effective use of physical memory. as figure 4.1 shows, when the process is smaller than physical memory, the entire process can be mapped to physical memory. when the process is too large to fit in physical memory, however, the process must be divided and the parts needed for execution mapped into physical memory when they are needed for execution [1]. this places a heavy burden on the process, which must be mapped to physical memory in a way that reflects the manner of its own execution. to lighten this burden, a virtual memory system was devised to handle all mapping to physical memory at once [2]. under the virtual memory system, a virtual memory that is sufficiently large relative to the size of the physical memory is provided. the process is then mapped onto this virtual memory. the process thus only needs to consider its operation in virtual memory. mapping from virtual to physical memory is performed by the mmu. the mmu is normally managed by the os, which swaps physical memory to enable smooth mapping onto physical memory of the virtual memory required by the process. swapping of physical memory occurs between it and secondary memory. this type of virtual memory system works at its best in a time sharing system (tss) that runs multiple processes simultaneously [3]. the multiple simultaneously running processes would not run efficiently if they each had to consider their own mapping to physical memory. to increase efficiency, a virtual memory system is used to decrease the burden on each process [4]. in this virtual memory system, each process is assigned to its own virtual memory. the mmu works to efficiently map multiple virtual memories to physical memory. so that additional processes do not mistakenly access another process? physical memory, the mmu has a memory protection function. when addresses are translated from virtual memory to physical memory using the mmu, the translation information is not always registered in the mmu and mistaken accesses of the virtual memory of other processes sometimes occurs. when it does, the mmu generates an exception, changes the physical memory mapping, and registers new address translation information.
66 the mmu functions can also be implemented using software alone, but translating by software every time the process accesses physical memory is inefficient. for that reason, a buffer for address translation is placed in hardware (the tlb) where frequently used address translation information can be stored. the tlb is basically a cache for address translation information. unlike the regular cache, however, swapping of address translation information when a mistake occurs in address translation (i.e., when an exception occurs) is done by software. this enables flexible management of memory by software. there are two systems of mapping virtual memory to physical memory in the mmu: fixed length address translation (paging) and variable length address translation (segmenting). in the paging system, address spaces of fixed sizes called pages (usually between 1 kbyte and 64 kbytes) are used as the unit of translation. in figure 4.1, address space in virtual memory is called virtual address space while address space in physical memory is called physical memory space. [1] [2] [4] [3] process 1 process 1 process 2 process 3 process 2 process 1 process 3 physical memory process 1 process 1 virtual memory virtual memory physical memory physical memory physical memory physical memory mmu mmu figure 4.1 mmu function
67 4.1.3 the sh7718r mmu virtual address map: the sh7718r supports 32-bit virtual addresses to access a 4-gbytes virtual address space that is divided into several areas. address space mapping is shown in figure 4.2. in the privileged mode, there are five areas, p0?4. the p0 and p3 areas are mapped onto physical address space in page units according to address translation table information. h'7f000000 through h'7fffffff in the p0 area, however, can be used as on-chip ram if so set in the cache control register (ccr). (see section 6, cache, for details.) if used as ram, mapping through the address translation table does not occur in the on- chip ram space. the write access is also set by the ccr, enabling selection between copy back and write through. mapping of the p1 area is fixed to physical address space (h'00000000 to h'1fffffff). in the p1 area, setting a virtual address msb (bit 31) to 0 generates the corresponding physical address. p1 area access can be cached, and the cache control register (ccr) is set to indicate whether to cache or not. write-back or write-through mode can be selected. mapping of the p2 area is fixed to physical address space (h'00000000 to h'1fffffff). in the p2 area, setting the top three virtual address msbs (bits 31, 30, and 29) to 0 generates the corresponding physical address. p2 area access cannot be cached. the p1 and p2 areas are not mapped by the address translation table, so the tlb is not used and no exceptions like tlb misses occur. initialization of the mmu control register, exception processing handling, and the like are located in the p1 and p2 areas. because the p1 area is cached, handlers that require high-speed processing are placed there. the p4 area is used for mapping control areas such as peripheral module registers. in user mode, the two gbytes of virtual address space from h'00000000 to h'7fffffff (u0) can be accessed. u0 is mapped onto physical address space in page units according to address translation table information. also, as in the p0 area, h'7f000000 through h'7fffffff can be used as on-chip ram if so set in the cache control register (ccr). if used as ram, mapping through the address translation table does not occur in the on-chip ram space. the 2 gbytes of virtual address space from h'80000000 to h'ffffffff cannot be accessed in user mode. attempting to do so creates an address error. the write access is also set by the ccr, enabling selection between copy back and write through.
68 address error h'ffffffff h'80000000 h'7f000000 h'00000000 h'ffffffff 0.5 gbytes, control space, noncached 0.5 gbytes, fixed physical space, noncached 0.5 gbytes, fixed physical space, cached (write-back/ write-through) 2 gbytes virtual space, cached (write-back/ write-through) 2 gbytes virtual space, cached (write-back/ write-through) 0.5 gbytes virtual space, cached (write- back/write-through) privileged mode h'a0000000 h'c0000000 h'e0000000 h'80000000 h'7f000000 h'00000000 user mode u0 space p4 space p3 space p2 space p1 space p0 space on-chip ram space on-chip ram space figure 4.2 virtual address space mapping physical address space : the sh7718r supports 32-bit physical addresses, but the top three bits are actually ignored and treated as shadows. for more information, see section 11, bus state controller. address translation: when the mmu is enabled, the virtual address space is divided into units called pages. physical addresses are translated in page units. address translation tables in external memory hold information such as the physical address that corresponds to the virtual address and memory protection codes. the tlb caches the address table data in external memory to speed up address translation. when an access to an area other than p4 occurs, there is no tlb access and the physical address is defined uniquely if the virtual address accessed belongs to areas p1 or p2. if it belongs to areas p0, p3, or u0, the tlb is searched by virtual address and, if that virtual address is registered in the tlb, the access hits the tlb. the corresponding physical address and the page control information are read from the tlb and the physical address is determined. if the virtual address is not registered in the tlb, a tlb miss exception occurs and processing shifts to the tlb miss handler. in the tlb miss handler, the tlb address translation table in
69 external memory is searched and the corresponding physical address and the page control information are registered in the tlb. after returning from the handler, the instruction that caused the tlb miss is re-executed. do not register address translation information in the tlb that will make the physical address fall between h'80000000 and h'ffffffff while the mmu is enabled. when the mmu is disabled, the virtual address is equal to the physical address without any changes. the sh7718r supports a 29-bit address space as its physical address space, so the top three bits of physical address are ignored and handled as shadow space (see section 11, bus state controller). for example, address h'00001000 of area p0, address h'80001000 of area p1, address h'a0001000 of area p2, and address h'c0001000 of area p3 are all mapped to the same physical memory. when these addresses are accessed when the cache is enabled, they are stored in addresses with the top three bits of the physical addresses masked to 0 to ensure data coherency in the cache's address array. single virtual memory mode and multiple virtual memory mode: there are two virtual memory modes selected by the mmu control register (mmucr): single virtual memory mode and multiple virtual memory mode. in single virtual memory mode, multiple processes run in parallel using the virtual address space exclusively and the physical address corresponding to a given virtual address is specified uniquely. in multiple virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a given virtual address may be translated into different physical addresses depending on the process. by the value set to the mmu control register, either single or multiple virtual mode is selected. the only difference in how single virtual memory mode and multiple virtual memory mode work is the system of tlb address comparison (see section 4.3.3, tlb address comparison, for details). asid: multiple virtual memory mode uses asids (address space ids) to distinguish multiple processes running simultaneously sharing virtual address space. the asid is 8 bits and can be set in the pteh within the mmu for the current process. with asids, the tlb need not be purged at every process switch. in single virtual memory mode, asids are used to protect memory for multiple processes running simultaneously through using virtual address space exclusively (see section 4.4.2, mmu software management). 4.1.4 register configuration table 4.1 lists the configuration of the mmu control register.
70 table 4.1 register configuration name abbreviation r/w size initial value* 1 address page table entry register high pteh r/w longword undefined h'fffffff0 page table entry register low ptel r/w longword undefined h'fffffff4 translation table base register ttb r/w longword undefined h'fffffff8 tlb exception address register tea r/w longword undefined h'fffffffc mmu control register mmucr r/w longword * 2 h'ffffffe0 notes: 1. initialized by a power-on reset or manual reset. 2. sv bit is undefined. all others are 0. 4.2 description of registers there are five registers for mmu processing. these are all peripheral module registers, so they are located in address space area p4 and can only be accessed from privileged mode by specifying the address. these registers consist of: 1. the page table entry high (pteh) register residing at address h'fffffff0 contains the virtual page number (vpn) and asid. when an mmu exception or address error exception occurs, the hardware sets the virtual address where the exception occurred as the vpn. when the page size is 4 kbytes, the vpn is the top 20 bits of the virtual address, but the top 22 bits of the virtual address are set. the vpn can also be modified by software. the number of the process currently running is set as the asid by software. this vpn and asid are registered in the tlb by the ldtlb instruction. 2. the page table entry low (ptel) register residing at address h'fffffff4 is used to store the physical page number and page management information registered in the tlb by the ldtlb instruction. the contents of this register do not change unless directed to by software. 3. the translation table base (ttb) register residing at address h'fffffff8, which may, for example, store the base address of the current page table. the data in the ttb does not change unless directed to by software. the ttb is available to the software for general purposes. 4. the tlb exception address (tea) register residing at address h'fffffffc, which stores the virtual address of any mmu exception or address error exception that occurs. the value is valid until the next exception or interrupt occurs. 5. the mmu control register (mmucr) residing at address h'fffffff0 sets the mmu as shown in figure 4.3. any program that modifies the mmucr should reside in the p1 or p2 area.
71 the mmu registers are shown in figure 4.3. 31 7 vpn pteh ptel asid 0 ppn 0 10 31 6 5 4 3 2 1 0 10 31 ttb ttb 0 31 virtual address causing mmu exception or address error exception tea 0 0 pr sz c d 8 9 7 v 0 0 sh 0 mmucr 0 31 sv rc 00 0 tf ix at 0: sv: rc: tf: ix: at: 6 5 4 3 2 1 8 7 reserved bits (except mmucr) : always read as 0. writes are ignored. reserved bits (mmucr) : bits other than bit 3 are always read as 0. bit 3 is a don't care bit. specify 0 when writing. single virtual memory mode bit. set to 1 for single virtual memory mode, 0 for multiple virtual memory mode. random counter. a 2-bit counter that is automatically updated by hardware when an mmu exception occurs following the rules described below. when a tlb miss exception occurs, all ways of the tlb entry for the virtual address that caused the exception are checked and rc is incremented by one if all ways are valid. when some ways are invalid, the smallest numbered way is set to the rc. when the mmu exception other than a tlb miss occurs, the way that caused the exception is set to the rc. tlb flush bit. write 1 to flush (clear all bits to 0). always reads 0. index mode bit. a logic 1 designates that the ex-ored value of bits 4? of the asid and vpn number bits 16?2 in the pteh are used to index the tlb; 0 specifies that only vpn number bits 16?2 are used to index the tlb. address translation bit. enables/disables mmu; 1 = mmu enabled; 0 = mmu disabled. figure 4.3 mmu register contents
72 4.3 tlb functions 4.3.1 tlb structure the tlb caches address translation table information located in external memory. the address translation table stores the virtual page number, the physical page number translated from the virtual page number, the asid, and the control information for the page. figure 4.4 shows the overall tlb configuration. the tlb is 4-way set associative with 128 entries (32 entries for each way). figure 4.5 shows the configuration of virtual addresses and tlb entries. ppn(31 10) entry 0 entry 1 address array data array entry 31 pr(1 0) sz ways 0 3 cdsh entry 0 entry 1 entry 31 vpn(31 17) ways 0 3 vpn(11 10) asid(7 0) v figure 4.4 overall configuration of the tlb
73 31 9 vpn virtual address (1-kbyte page) virtual address (4-kbyte page) tlb entry offset vpn vpn(31 17) vpn(11 10) asid sh sz v pr ppn c d offset 0 10 31 11 0 (15) (2) (2) (22) (8) (1) (1) (1) (1) (1) 12 vpn: asid: sh: sz: v: ppn: pr: c: d: virtual page number. the top 20 bits of virtual address for a 4-kbyte page or the top 22 bits of virtual address for a 1-kbyte page. since vpn(16 12) are used as the index number, they are not stored in the tlb entry. address space identifier. indicates the process that can access the virtual page. in single virtual memory mode and user mode or in multiple virtual memory mode, the asid in pteh is compared in address comparisons if the sh bit is 0. share status bit; 0 = page not shared between processes; 1 = page shared between processes. page size bit; 1 = 4-kbyte page; 0 =1-kbyte page. valid bit. indicates if entry is valid; 1 = valid; 0 = invalid. cleared to 0 by a power- on reset; not changed by a manual reset. physical page number. top 22 bits of physical address. ppn(11 10) are not used with 4-kbyte pages. watch for synonym problems with 1-kbyte pages (see section 4.4.4, avoiding synonym problems). protection key field. 2-bit field encoded to define the access rights to the page. 00: read-only in privileged mode. 01: read and write in privileged mode. 10: read-only in privileged and user mode. 11: read and write in privileged and user mode. cacheable bit. indicates if page resides in cacheable area of memory; 1 = cacheable; 0 = noncacheable. dirty bit. indicates if the page has been written to; 1 = written to, 0 = not written to. figure 4.5 virtual address and tlb structure
74 4.3.2 creating tlb index numbers the tlb uses a 4-way set associative scheme, so entries must be selected by index. vpn bits 16 to 12 and the pteh? asid (4?) are used as index numbers. the index address can be generated in two different ways depending on the setting of the ix bit in the mmucr: 1. when ix = 1, vpn bits 16?2 are ex-ored with asid bits 4? to generate the index number 2. when ix = 0, vpn bits 16?2 are used as the index number. the first method is used to prevent lowered tlb efficiency when multiple processes run simultaneously in the same virtual address space (multiple virtual memory mode) and a specific entry is selected by multiple processes by indexing. figures 4.6 and 4.7 illustrate the indexing schemes. 31 17 16 12 11 0 31 exclusive-or asid (4 0) ways 0 3 virtual address pteh register 10 vpn 0 asid 70 index ppn(31 10) 0 address array data array 31 pr(1 0) sz c d sh 0 31 vpn(31 17) vpn(11 10) asid(7 0) v figure 4.6 tlb indexing (ix = 1)
75 31 17 16 12 11 0 virtual address 0 31 index ways 0 3 ppn(31 10) 0 address array data array 31 pr(1 0) sz c d sh vpn(31 17) vpn(11 10) asid(7 0) v figure 4.7 tlb indexing (ix = 0) 4.3.3 tlb address comparison tlb address comparison is used when fetching instructions from programs in external memory and when accessing data in external memory. the virtual page number (vpn) and asid are used for address comparison. the vpn of the virtual address that accesses external memory is compared to the vpn of the indexed tlb entry. the asid within the pteh is compared to the asid of the indexed tlb entry. all four ways are searched simultaneously. if the compared values match and the indexed tlb entry is valid (v bit = 1), the tlb hit is registered. configure the software to ensure that multiple ways are not tlb hit simultaneously. should this occur, hardware operation cannot be guaranteed. for example, make sure that the software is set so that only the process with asid=h'ff is hit for two tlb entries with the same vpn where one shares (sh=1) and the other does not (sh=0). otherwise, when the asid in pteh changes to h'ff, there is the possibility of a tlb hit to two ways simultaneously. do not make these kinds of settings using software.
76 the object compared varies depending on the page management information (sz, sh) in the tlb entry. it also varies depending on whether the system supports multiple virtual memory or single virtual memory. the page size bit (sz) determines whether vpn (11?0) are compared. vpn (11?0) are compared for 1 kbyte pages (sz = 0) but not for 4 kbytes pages (sz = 1). the sharing information bit (sh) determines whether the pteh.asid and the asid in the tlb entry are compared. asids are compared when there is no sharing between processes (sh = 0) but not when there is sharing (sh = 1). when single virtual memory mode (mmucr.sv = 1) and privileged mode are engaged (sr.md = 1), all process resources can be accessed because asids are not compared. the objects of address comparison are shown in figure 4.8. bits compared: vpn(31 17) vpn(11 10) sz = 0? yes no yes (1 kbyte) no (4 kbytes) bits compared: vpn(31 17) bits compared: vpn(31 17) vpn(11 10) asid(7 0) sz = 0? yes (1 kbyte) no (4 kbytes) bits compared: vpn(31 17) asid(7 0) sh = 1 or (sr.md = 1 and mmucr.sv = 1)? figure 4.8 objects of address comparison 4.3.4 page management information in addition to the sh and sz bits, the page management information of tlb entries also includes d, c, and pr bits.
77 the d bit of a tlb entry indicates if the page is dirty (i.e., has been written to). if the d bit is 0, an attempt to write to the page results in an initial page write exception. for physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. to record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. the c bit in the entry indicates whether the referenced page resides in a cacheable or non- cacheable area of memory. the pr field specifies the access rights for the page in privileged and user modes and is used to protect memory. attempts at prohibited accesses result in tlb protection violation exceptions. table 4.2. shows the access states of the d, c, and pr bits. table 4.2 access states of the d, c, and pr bits privileged mode user mode bits read write read write d bit 0 ok initial page write exception ok initial page write exception 1ok ok ok ok c bit 0 ok (no caching) ok (no caching) ok (no caching) ok (no caching) 1 ok (caching) ok (caching) ok (caching) ok (caching) pr bits 00 ok tlb protection violation exception tlb protection violation exception tlb protection violation exception 01 ok ok tlb protection violation exception tlb protection violation exception 10 ok tlb protection violation exception ok tlb protection violation exception 11 ok ok ok ok 4.4 mmu functions 4.4.1 mmu hardware management there are two types of mmu hardware management.
78 1. decoding a virtual address accessed from a process and translating the address by controlling the tlb according to mmucr settings. 2. receiving page management information and hit information from the tlb when the address is translated and checking for mmu exceptions and for whether the cache was accessed (c bit). see section 4.5, mmu exceptions, for a description of this method of checking and hardware processing. 4.4.2 mmu software management there are three types of mmu software management. mmu register settings : set the mmucr in areas p1 and p2, which do not translate addresses. also, since changing the sv and ix bits changes the address translation system, simultaneously write a 1 to the tf bit to flush the tlb. when the mmu is disabled with an at bit of 0, no mmu exceptions occur, so it should always be disabled for software that does not use the mmu. registering, deleting, and reading tlb entries : data can be registered in a tlb entry either by using the ldtlb instruction or by writing directly to memory-mapped tlb. tlb entries can be deleted or read by accessing the memory-mapped tlb. see section 4.4.3, mmu instructions, for details about the ldtlb instruction and section 4.6, memory-mapped tlb, for details about the memory-mapped tlb. mmu exception processing : information set through the hardware is restored to the original when an mmu exception occurs. see section 4.5, mmu exceptions, for more information. when single virtual memory mode is used, the share bit (sh) can be set to 0 and all tlb entries registered to create a state that enables access to all physical memory only in privileged mode. this strengthens protection of memory between processes and creates a special access level for privileged mode. synonym problems may occur when registering 1 kbyte page tlb entries. see section 4.4.4, avoiding synonym problems. 4.4.3 mmu instructions (ldtlb) the load tlb (ldtlb) instruction is used to register tlb entries. when the mmucr.ix bit is 0, the ldtlb instruction uses the vpn (16?2) specified in pteh as the index number and changes the tlb entry of the way specified by the mmucr.rc bit to the values specified in pteh and ptel. when the mmucr.ix bit is 1, the ldtlb instruction ex-ors the vpn (16 to 12) specified in pteh and the asid (4?) in the pteh for the index number. figure 4.9 shows the operation of the ldtlb instruction when the mmucr.ix bit is 0.
79 the virtual page number of the virtual address that causes an mmu exception is set by hardware in the pteh when the exception occurs. ways are also set in the mmucr.rc bit according to the rules described in figure 4.4. for this reason, if an ldtlb instruction is called in an mmu exception processing routine with only ptel set, the tlb entry can be registered. rewriting the pteh and mmucr.rc bit with software enables rewriting of any tlb entry. the ldtlb instruction changes the address translation information, so it may degrade address translation information that is currently executing when it is called in the p0, u0, or p3 areas. be sure to call it in the p1 or p2 areas. instructions that involve access of the p0, u0, or p3 area (e.g., the rte instruction) must be separated from the ldtlb instruction by at least one instruction. 0 31 ppn(31 10) 0 31 pr(1 0) sz c d sh vpn(31 17) vpn(11 10) asid(7 0) v ppn 0 v 0pr sz c dsh d sv 0 0 0 rc 0 tf ix at vpn vpn 0 asid 31 31 31 17 12 10 10 80 0 90 mmucr way selection index pteh register ptel register ways 0 3 write write address array data array figure 4.9 operation of the ldtlb instruction
80 4.4.4 avoiding synonym problems synonym problems may occur when 1-kbyte pages are registered in tlb entries. synonym problems occur when multiple virtual addresses are mapped to a single physical address and the same physical address data is registered in multiple cache entries, making it impossible to guarantee the consistency of the data. figure 4.10 shows why this problem only occurs when 1-kbyte pages are used. the sh7718r creates index numbers using virtual address (10?) to speed up cache operations. when 4-kbytes pages are used, (10?) of the virtual address are included in the offset and are not objects of address translation, so they are the same as physical address (10?). the cache tag address is the physical address for comparisons of addresses in the cache and registration in address arrays, so (31?0) of the physical address are registered. when 1-kbyte pages are used, (10?) of the virtual address are used to create the cache? index number. for 1-kbyte pages, however, virtual address (10) is an object of address translation, so it is not always the same as physical address (10). for this reason, the physical address is registered in a different entry from the cache address array? index number that indicates the physical address. for example, in a 1-kbyte page tlb entry, two tlb entries can be registered to translate as follows: virtual address 1 h'00000000 physical address h'00000400 virtual address 2 h'00000400 physical address h'00000400 virtual address 1 is registered in cache entry h'00 while virtual address 2 is registered in entry h'40. despite the identical physical address, they are registered in different cache entries, so coherency will be lost if either virtual address is written to even once. for this reason, when registering a 1-kbyte tlb entry, do not register the same virtual address (10) if the physical address is the same as one already used by another tlb entry.
81 vpn ppn ppn vpn 31 12 11 10 0 31 12 11 10 0 31 9 10 0 31 9 10 0 using 4-kbyte page virtual address virtual address (10 4) virtual address (10 4) offset offset offset offset physical address physical address (31 10) physical address (31 10) using 1-kbyte page virtual address physical address cache address array cache address array figure 4.10 synonym problems 4.5 mmu exceptions there are four mmu exceptions: tlb miss, tlb protection violation, tlb invalid, and initial page write. 4.5.1 tlb miss a tlb miss results when the virtual address and the address array of the selected tlb entry are compared and no match is found. tlb miss exception processing includes both hardware and software operations.
82 hardware operations: in a tlb miss, the sh7718r hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written into the pteh register. 2. the virtual address causing the exception is written into the tea register. 3. either exception code h'040 for a load access, or h'060 for a store access, is written to the expevt register. 4. the value of the pc indicating the address of the instruction in which the exception occurred is written into the save program counter (spc). if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written into the spc. 5. the contents of the status register (sr) at the time of the exception are written into the save status register (ssr). 6. the mode (md) bit in sr is set to a logic one to place the sh7718r in privileged mode. 7. the block (bl) bit in sr is set to a logic one to mask any further exception requests. 8. the register bank (rb) bit of the sr is set to 1. 9. all ways of the tlb entry for the virtual address that caused the exception are checked and the random counter (rc) of the mmu control register (mmucr) is incremented by 1 when all ways are valid. when some entries indexed are invalid, the smallest numbered of the ways is set to the rc. 10. execution branches to the address obtained by adding the value of vbr contents and h'00000400 to invoke the tlb miss handler routine. software (tlb miss handler) operations: the software searches the page tables in external memory and allocates the required page table entry. to retrieve the required page table entry, the software must execute the following operations: 1. write the values of the physical page number (ppn) field and the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (sh), and valid (v) bits of the page table entry recorded in the address translation table in external memory into the ptel register. 2. if using software to select ways for entry replacement, write the desired value into the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the return from exception handler (rte) instruction to terminate the handler routine and return to the instruction stream. separate the ldtlb and rte instructions by at least one other instruction. 4.5.2 tlb protection violation a tlb protection violation exception results when the virtual address and the address array of the selected tlb entry are compared and a valid entry is found to match, but the type of access is not
83 permitted by the access rights specified in the pr field. tlb protection violation exception processing includes both hardware and software operations. hardware operations: in a tlb protection violation exception, the sh7718r hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written into the pteh register. 2. the virtual address causing the exception is written into the tea register. 3. either exception code h'0a0 for a load access, or h'0c0 for a store access, is written to the expevt register. 4. the value of the pc indicating the address of the instruction in which the exception occurred is written into spc. (if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written into spc.) 5. the contents of sr at the time of the exception are written into ssr. 6. the md bit in sr is set to a logic one to place the sh7718r in privileged mode. 7. the bl bit in sr is set to a logic one to mask any further exception requests. 8. the register bank (rb) bit of the sr is set to 1. 9. the way that generated the exception is set in the random counter (rc) of the mmucr. 10. execution branches to the address obtained by adding the value of vbr contents and h'00000100 to invoke the tlb protection violation exception handler routine. software (tlb protection violation handler) operations: the software resolves the tlb protection violation and issues the rte (return from exception handler) instruction to terminate the handler routine and return to the instruction stream. separate the ldtlb and rte instructions by at least one other instruction. 4.5.3 tlb invalid exception a tlb invalid exception results when the virtual address is compared to a selected tlb entry address array and a match is found but the entry was not valid (a v bit of 0). tlb invalid exception processing includes both hardware and software operations. hardware operations: in a tlb invalid exception, the sh7718r hardware executes a set of prescribed operations, as follows: 1. the vpn number of the virtual address causing the exception is written into the pteh register. 2. the virtual address causing the exception is written into the tea register. 3. the way number causing the exception is written into rc of the mmucr. 4. either exception code h'040 for a load access, or h'060 for a store access, is written to the expevt register.
84 5. the value of the pc indicating the address of the instruction in which the exception occurred is written into the spc. if the exception occurred in a delay slot, the pc value indicating the address of the delayed branch instruction is written into the spc. 6. the contents of the sr at the time of the exception are written into the ssr. 7. the mode (md) bit in the sr is set to one to place the sh7718r in privileged mode. 8. the block (bl) bit in the sr is set to one to mask any further exception requests. 9. the register bank (rb) bit in the sr is set to one. 10. execution branches to the address obtained by adding the value of vbr contents and h'00000100 and the tlb protection violation handler starts. software (tlb invalid exception handler) operations: the software searches the page tables in external memory and assigns the required page table entry. upon retrieving the required page table entry, the software must execute the following operations: 1. write the values of the physical page number (ppn) field and the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (sh), and valid (v) bits of the page table entry recorded in external memory into the ptel register. 2. if using software to select the way for entry replacement, write the desired value into the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the rte instruction to terminate the handler routine and return to the instruction stream. separate the ldtlb and rte instructions by at least one other instruction. 4.5.4 initial page write an initial page write exception results in a write access when the virtual address and the address array of the selected tlb entry are compared and a valid entry with the appropriate access rights is found to match but the d (dirty) bit of the entry is a logic zero (page cannot be written to). initial page write exception processing includes both hardware and software operations. hardware operations: in an initial page write exception, the sh7718r hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. exception code h'080 is written into the expevt register. 4. the value of the pc indicating the address of the instruction in which the exception occurred is written to spc. if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written to spc. 5. the contents of sr at the time of the exception are written to ssr. 6. the md bit in sr is set to a logic one to place the sh7718r in privileged mode.
85 7. the bl bit in sr is set to a logic one to mask any further exception requests. 8. the register bank (rb) bit of the sr is set to 1. 9. the way that caused the exception is set in the random counter (rc) of the mmucr. 10. execution branches to the address obtained by adding the value of vbr contents and h'00000100 to invoke the user-written initial page write exception handler routine. software (initial page write handler) operations: the software must execute the following operations: 1. retrieve the required page table entry from external memory. 2. set the d bit of the page table entry in external memory to a logic one. 3. write the value of the ppn field and the pr, sz, c, d, sh, and v bits of the page table entry in external memory into the ptel register. 4. if using software to select the way for entry replacement, write the desired value into the rc field in mmucr. 5. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 6. issue the rte instruction to terminate the handler routine and return to the instruction stream. separate the ldtlb and rte instructions by at least one other instruction. figure 4.11 shows the flow of mmu exceptions.
86 start tlb miss exception initial page write pr? pr? yes sh = 0 and (mmucr.sv = 0 or sr.md = 0)? vpns and asids match? vpns match? no yes yes yes yes user or privileged? d = 1? c = 1? v = 1? no no user mode privileged mode no no tlb protection violation tlb protection violation cache access w 00/01 10 01/11 00/10 11 ww w rr rr r/w? r/w? r/w? r/w? tlb invalid exception memory access no (noncacheable) yes (cacheable) figure 4.11 mmu exception generation flowchart
87 4.5.5 processing when an mmu exception occurs figure 4.12 shows the mmu exception during instruction fetch. id ex ma wb if id nop ex ma wb id ex ma wb id ex ma nop wb handler transition processing mmu exception handler : stage causing exception if: id: ex: ma: wb: nop: instruction fetch instruction decoding instruction execution memory access write back no operation if figure 4.12 mmu exception signals during instruction fetch figure 4.13 shows mmu exception during data access.
88 if id ex if id ex if id if id ex ma wb id ex ma wb id ex ma wb id ex ma nop wb nop handler transition processing mmu exception handler : stage causing exception : canceled stages of instructions already executing if: id: ex: ma: wb: nop: instruction fetch instruction decoding instruction execution memory access write back no operation ma wb ma wb ex ma wb figure 4.13 mmu exception signals during data access 4.6 memory-mapped tlb to manage tlb operations by software, the tlb can be read and written using the mov instruction in privileged mode. the tlb is assigned to virtual address space p4. the tlb address array (vpn, v bit, and asid) is mapped to h'f2000000 to h'f2ffffff and the data array (ppn, pr, sz, c, d, and sh bits) is mapped to h'f3000000 to h'f3ffffff. the address array? v bit can also be accessed from the data array. access sizes are longword for both address array and data array. 4.6.1 address array the address array is assigned to h'f2000000 to h'f2ffffff. to access an address array, the 32-bit address section (for read/write) and 32-bit data section (for write) must be specified. the
89 address section specifies information for selecting the entry to be accessed; the data section specifies the vpn, v bit and asid to be written to the address array (figure 4.14 (1)). in the address section, specify the index address for selecting the entry (vpn bits 16?2) in bits (16?2) of the address section, the w for selecting the way in bits (9?) of the address section, and h'f2 to indicate address array access in bits (31?4). the ix bit of the mmucr indicates whether an ex-or is taken of vpn (16?2) and the pteh register? asid (4?) for the index address. when writing, specify bit 7 as the associative (a) bit. the a bit indicates whether addresses are compared during writing. when the a bit is 1, the vpns of the four entries selected by the index addresses are compared to the vpn to be written into the address array specified in the data section. writing takes place to the way that has a hit. when a miss occurs, nothing is written to the address array and no operation occurs. the way number specified in bits 9? is not used. the item compared is determined by the sz and sh bits of the entry selected by the index address, the sv bit of the mmucr, and the md bit of the sr, just as in ordinary operations (see section 4.3.3). when the a bit is 0, it is written to the entry selected by the index address and way without comparing addresses. when reading, the vpn, v bit, and asid of the entry specified by the index address and way are read in the format of the data section in figure 4.14 without comparing addresses. bits (16?2) of the data section read 0. to invalidate a specific entry, specify the entry and write 0 to its v bit. when 1 is specified for the a bit, only the desired vpn entry is invalidated. 4.6.2 data array the data array is assigned to h'f3000000 to h'f3ffffff. to access a data array, the 32-bit address section (for read/write), and 32-bit data section (for write) must be specified. the address section specifies information for selecting the entry to be accessed; the data section specifies the longword data to be written to the data array (figure 4.14 (2)). the bit structure of the longword data is the same as the ptel. in the address section, specify the index address for selecting the entry (vpn bits 16?2) in bits (16?2) of the address section, the w for selecting the way in bits (9?) of the address section, and h'f3 to indicate data array access in bits (31?4). the ix bit of the mmucr indicates whether an ex-or is taken of vpn (16?2) and the pteh register? asid (4?) for the index address. both reading and writing use the longword of the data array specified by the index address and way.
90 vpn 31 23 1 1 1 1 0 0 1 0 ***** * ** ** * *** * ***** * 16 1. tlb address array access address section data section address section data section address section data section w 0 31 24 17 17 17 vpn 16 0 vpn asid 0 v 00 vpn 31 23 24 1 1 1 1 0 0 1 1 16 17 w 0 31 10 ppn 8 9 7654 3 2 1 0 x v xx vpn 31 24 23 16 read write 2. tlb data array access 12 10 11 8 976 12 10 11 8 97 12 10 11 8 97 12 10 11 8 97 0 wa 1 1 1 1 0 0 1 0 31 10 12 asid vpn vpn 8 9 17 16 7 0 v d c sh pr sz ppn: pr: c: sh: vpn: x: w: physical page number protection key data cacheable bit share bit virtual page number 0 for read, don t-care for write way (00: way 0, 01: way 1, 10: way 2, 11: way 3) v: sz: d: * : valid bit page size bit dirty bit don t care bit ............ ........ ....... ............ ............ ............ ............ ............ read/write vpn: v: a: w: virtual page number valid bit associative bit way (00: way 0, 01: way 1, 10: way 2, 11: way 3) asid: * : address space id don t care bit 0 figure 4.14 specifying address and data for memory-mapped tlb access 4.6.3 examples invalidating specific entries: specific tlb entries can be invalidated by writing 0 to the entry? v bit. when the a bit is 1, the vpn and asid specified by the write data are compared to the vpn and asid within the tlb entry selected by the index address and data is written to the
91 matching way. if no match is found, there is no operation. in the following example, r0 specifies the write data and r1 specifies the address. ;r0 = h'1547 381c r1 = h'f201 3080 ;mmucr.ix = 0 ;entry corresponding to vpn(31-17) = b'0001 0101 0100 011 vpn(11-10) = b'10 asid = b'0001 1100 is associated with the entry selected by the index mov.l r0,@r1 reading a data array: this example reads the data array of a specific tlb entry. the register is read in the bit order indicated in the data section in figure 4.14 (2). in the following example, r0 specifies the address and the data section of a selected entry is read to r1. ;r0 = h'f300 4300 vpn(16-12) = b'0 0100 way 3 mov.l @r0,r1 4.7 cautions use instructions that manipulate the sr register? md and bl bits (ldc rm, sr instruction, ldc @rm+, sr instruction, and rte instruction), instructions that follow them, and ldtlb instructions with the tlb disabled or in fixed physical address space (p1 or p2).
93 section 5 exception processing 5.1 overview 5.1.1 features exceptions are deviations from normal program execution that require special handling. the processor responds to an exception by aborting execution of the current instruction (execution is allowed to continue to completion in all interrupt requests) and passing control from the instruction stream to the appropriate user-written exception handling routine. here, all exceptions other than resets and interrupts will be called general exceptions. there are thus three types of exceptions: resets, general exceptions, and interrupts. 5.1.2 register configuration table 5.1 lists the register configuration for exception processing. table 5.1 register configuration register abbr. r/w size initial value address trapa exception register tra r/w longword undefined h'ffffffd0 exception event register expevt r/w longword power-on reset: h'000 manual reset: h'020 h'ffffffd4 interrupt event register intevt r/w longword undefined h'ffffffd8 5.2 exception processing function 5.2.1 exception processing flow usually the contents of program counter (pc) and status register (sr) are saved in the saved program counter (spc) and saved status register (ssr), respectively, and execution of the exception handler is invoked from a vector address. the return from exception handler (rte) instruction is issued by the exception handler routine at the completion of the routine, restoring the contents of the pc and sr to return to the processor status at the point of interruption and the address where the exception occurred. a basic exception processing sequence consists of the following operations: 1. the contents of pc and sr are saved in spc and ssr, respectively.
94 2. the block (bl) bit in sr is set to a logic one, masking any subsequent exceptions. 3. the mode (md) bit in sr is set to a logic one to place the sh7718r in privileged mode. 4. the register bank (rb) bit in sr is set to a logic one. 5. an encoded value identifying the exception event is written into bits 11? of the exception event (expevt) or interrupt event (intevt) register. 6. instruction execution jumps to the designated exception processing vector address to invoke the handler routine. 5.2.2 exception processing vector table the reset vector address is fixed at h'a0000000. general exceptions and interrupts are assigned offsets from the vector base address by software. translation look-aside buffer (tlb) miss traps have an offset from the vector base address of h'00000400. the vector address offset for general exception events other than tlb miss traps is h'00000100. the interrupt vector address offset is h'00000600. the vector base address is loaded into the vector base register (vbr) by software. the vector base address should reside in p1 or p2 fixed physical address space. figure 5.1 shows the relationship between the vector base address, the vector offset, and the vector table. vbr + vector offset h'a0000000 vector address vector base register figure 5.1 vector addresses in table 5.2, exceptions and their vector addresses are listed by exception type, instruction completion status, relative acceptance priority, relative order of occurrence within an instruction execution sequence and vector address.
95 table 5.2 vectored exception events exception type completion status exception event priority* 1 exception order vector address vector offset reset aborted power-on 1 h'a00000000 manual reset 1 h'a00000000 general exception aborted and retried address error (instruction access) 2 1 h'00000100 events tlb miss (instruction access) 2 2 h'00000400 tlb invalid (instruction access) 2 3 h'00000100 tlb protection violation (instruction access) 2 4 h'00000100 reserved instruction code exception 2 5 h'00000100 illegal slot instruction exception 2 5 h'00000100 address error (data access) 2 6 h'00000100 tlb miss (data access) 2 7 h'00000400 tlb invalid (data access) 2 8 h'00000100 tlb protection violation (data access) 2 9 h'00000100 fpu exception 2 10 h'00000100 initial page write 2 10 h'00000100 completed unconditional trap (trapa instruction) 2 5 h'00000100 user breakpoint trap 2 n* 2 h'00000100
96 table 5.2 vectored exception events (cont) exception type completion status exception event priority* 1 exception order vector address vector offset interrupt requests completed nonmaskable interrupt 3 h'00000600 external hardware interrupt 4* 3 h'00000600 peripheral module interrupt 4* 3 h'00000600 notes: 1. priorities are indicated from high to low, 1 being highest and 4 being lowest. 2. the user can define the break point traps. 1 is a break point before instruction execution and 11 is a break point after instruction execution. for an operand break point, use 11. 3. use software to specify relative priorities of external hardware interrupts and peripheral module interrupts. 5.2.3 receiving interrupt causes processor resets and interrupts are asynchronous events unrelated to the instruction stream. all exception events are prioritized to establish an acceptance order whenever two or more exception events occur simultaneously. the power-on reset and manual reset may not occur simultaneously, so they have the same priority. all general exception events occur in a relative order in the execution sequence of an instruction (i.e., execution order), but are handled at priority level 2 in instruction-stream order (i.e., program order). in other words, an exception detected in a preceding instruction is accepted prior to an exception detected in a subsequent instruction. three general exception events (reserved instruction code exception, unconditional trap, and illegal slot instruction exception) are detected in the decode stage of different instructions and are mutually exclusive events in the instruction pipeline. they have the same execution priority. figure 5.2 shows the order of general exception acceptance sequence.
97 if instruction n id ex ma tlb miss (data access) wb if instruction n + 1 instruction n + 2 id ex ma tlb miss (instruction access) wb if id ex ma rie (reserved instruction exception) wb pipeline sequence: tlb miss (instruction n) reexecution of instruction n 1 2 3 tlb miss (instruction n + 1) reexecution of instruction n + 1 rie (instruction n + 2) if id ex ma wb = instruction fetch = instruction decode = instruction execution = memory access = write back handling order: program order: tlb miss (instruction n + 1) tlb miss (instruction n) and rie (instruction n + 2) = simultaneous detection detection order: figure 5.2 example of acceptance order of general exception events
98 5.2.4 exception codes table 5.3 lists the exception codes written into bits 11? of the expevt register (for reset or general exception events) or the intevt register (for general interrupt requests) to identify each specific exception event. an additional exception register, the trapa (tra) register, is used to hold the 8-bit immediate data in an unconditional trap (trapa instruction). table 5.3 exception codes exception type exception event module factor exception code reset power-on h'000 manual reset h'020 general tlb miss/invalid (load) h'040 exception tlb miss/invalid (store) h'060 events initial page write h'080 tlb protection violation (load) h'0a0 tlb protection violation (store) h'0c0 address error (load) h'0e0 address error (store) h'100 fpu exception h'120 unconditional trap (trapa instruction) h'160 reserved instruction code h'180 illegal slot instruction h'1a0 user breakpoint trap h'1e0 interrupt nonmaskable interrupt h'1c0 requests external hardware interrupts irl3 irl0 = irl0 = irl0 = irl0 = irl0 = irl0 = irl0 = irl0 = irl0 = irl0 =
99 table 5.3 exception codes (cont) exception type exception event module factor exception code interrupt external hardware interrupts (cont) irl3 irl0 = irl0 = irl0 = irl0 = irl0 = exceptions and interrupts are accepted when the sr register? bl bit is 0. if a general exception occurs when the bl bit in sr is one, cpu internal registers go into the reset state; other module registers branch to the same address used for resets in a state where they hold the contents before the ordinary exception occurred (h'a0000000). if an interrupt occurs when bl = 1, the request held pending and not accepted until the bl bit is cleared to a logic zero by software. to enable overlapping exception processing to be accepted, spc and ssr must be saved and the bl bit in sr cleared to zero.
100 5.2.6 returning from exception processing use the rte instruction to return from exception processing. the rte instruction saves the pc to spc and sr to ssr, branches to the spc address, and returns from exception processing. if spc and ssr were saved to external memory, call the rte instruction after changing the sr.bl bit to 1 and returning them. 5.3 register description there are three registers for exception processing. they are peripheral module registers, so they are located in the p4 area. they can only be accessed in privileged mode by specifying an address. exception event register (expevt) : resides at h'ffffffd4. composed of 12 bits of exception code. the exception code placed in expevt is the exception code from resets and ordinary exception events. the exception code is set automatically by hardware when the exception occurs. expevt can be changed from software. interrupt event register (intevt) : resides at h'ffffffd8. composed of 12 bits of exception code. the exception code placed in intevt is the exception code from interrupt requests. the exception code is set automatically by hardware when the exception occurs. intevt can be changed from software. trapa exception register (tra) : resides at h'ffffffd0. composed of the 8 bits of immediate data from the trapa instruction. tra is set automatically by hardware when the trapa instruction is executed. tra can be changed from software. the bit configurations of the expevt, intevt, and tra registers are diagrammed in figure 5.3. 31 0 0 exception code imm 00 11 12 0 expevt register and intevt register 31 00 9 10 2 0 tra 0: imm: reserved bits, always read as zero. 8-bit immediate data in trapa instruction. figure 5.3 bit configurations of expevt, intevt, and tra registers
101 5.4 exception handler operation 5.4.1 reset the reset sequence is used to power up the sh7718r or restart it from the initialization state. the reset signal is sampled every clock cycle, and if a power-on reset is asserted, the reset sequence is initiated immediately, canceling all current operations (except the rtc) and any pending events. for a manual reset, some processing for ensuring data in external memory continues. the breq (bus request) signal is used to distinguish between power-on reset (high-level input) and manual reset (low-level input). the reset sequence consists of the following operations: 1. the md bit in sr is set to a logic one to place the sh7718r in privileged mode. 2. the bl bit in sr is set to a logic one, masking any subsequent exceptions. 3. the rb bit in sr is set to a logic one. 4. an encoded value of h'000 in a power-on reset or h'020 in a manual reset is written into bits 11? of the expevt register to identify the exception event. 5. instruction execution jumps to the user-written handler routine at address h'a0000000. 5.4.2 interrupts interrupts are accepted at the completion of the current instruction. the interrupt acceptance sequence consists of the following operations: 1. the contents of the pc and sr are saved in spc and ssr, respectively. 2. the bl bit in sr is set to a logic one, masking any subsequent exceptions. 3. the md bit in sr is set to a logic one to place the sh7718r in privileged mode. 4. the rb bit in sr is set to a logic one. 5. an encoded value identifying the exception cause is written into bits 11? of the intevt register. 6. instruction execution jumps to the vector location designated by the sum of the value of the contents of the vector base register (vbr) and h'00000600 to invoke the handler routine. 5.4.3 general exceptions when the sh7718r encounters any exception condition other than a reset or interrupt request, it executes the following operations: 1. the contents of the pc and sr are saved in spc and ssr, respectively. 2. the bl bit in sr is set to a logic one, masking any subsequent exceptions. 3. the md bit in sr is set to a logic one to place the sh7718r in privileged mode. 4. the rb bit in sr is set to a logic one.
102 5. an encoded value identifying the exception cause is written into bits 11? of the expevt register. 6. instruction execution jumps to the vector location designated by either the sum of the vector base address and offset h'00000400 in the vector table in a tlb miss trap, or by the sum of the vector base address and offset h'00000100 for exceptions other than tlb miss traps, to invoke the handler routine. 5.5 individual exception operations this section describes conditions when specific exception processing runs and the processor operations. 5.5.1 resets 1. power-on resets conditions: breq pin high and reset low operations: expevt set to h'000, vbr and sr initialized, branch to pc = h'a0000000 occurs. initialization sets the vbr register to h'0000000. in the sr, the md, rb, and bl bits are set to 1 and the interrupt mask bits (i3-i0) are set to b'1111. the cpu and on-chip peripheral modules are initialized. for more information, see the register descriptions. be sure to use a power-on reset when the power is turned on. 2. manual resets conditions: breq pin low and reset low operations: expevt set to h'020, vbr and sr initialized, branch to pc = h'a0000000 occurs. initialization sets the vbr register to h'0000000. in the sr, the md, rb, and bl bits are set to 1 and the imask field (i3-i0) is set to b'1111. the cpu and on-chip peripheral modules are initialized. for more information, see the register descriptions.
103 table 5.4 resets transition conditions for reset state internal state on-chip peripheral type breq reset cpu module power-on reset high low initialization see register manual reset low low initialization description in appropriate section 5.5.2 general exceptions 1. tlb miss conditions: comparison of tlb addresses shows no address match operations: the virtual address (32 bits) that caused the exception is set to the tea and the corresponding virtual page number (22 bits) is set to pteh (31?0). the asid of the pteh indicates the asid at the time the exception occurred. the rc bit of the mmucr is incremented by one for replacement when all ways are valid or set with priority starting at way 0 if any ways are not valid. the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. when the exception occurred during a read, h'040 is set to expevt; when the exception occurred during a write, h'060 is set to expevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0400. to speed up tlb miss processing, the offset differs from other exceptions. 2. tlb invalid conditions: comparison of tlb addresses shows address match but v = 0 operations: the virtual address (32 bits) that caused the exception is set to the tea and the corresponding virtual page number (22 bits) is set to pteh (31?0). the asid of the pteh indicates the asid at the time the exception occurred. the way that generated the exception is set to the rc bit of the mmucr. the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. when the exception occurred during a read, h'040 is set to expevt; when the exception occurred during a write, h'060 is set to expevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0100. 3. tlb initial write conditions: a hit occurred to the tlb for a store access, but d = 0 this occurs for initial writes to the page registered by the load.
104 operations: the virtual address (32 bits) that caused the exception is set to the tea and the corresponding virtual page number (22 bits) is set to pteh (31?0). the asid of the pteh indicates the asid at the time the exception occurred. the way that generated the exception is set to mmucr.rc. the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. h'080 is set to expevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0100. 4. tlb protection conditions: table 5.5 lists the conditions when a hit access violates this tlb protection information (pr bits): table 5.5 tlb protection conditions pr privileged mode user mode 00 only read enabled no access 01 read/write enabled no access 10 only read enabled only read enabled 11 read/write enabled read/write enabled operations: the virtual address (32 bits) that caused the exception is set to the tea and the corresponding virtual page number (22 bits) is set to pteh (31?0). the asid of the pteh indicates the asid at the time the exception occurred. the way that generated the exception is set to the rc bit of the mmucr. the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. when the exception occurred during a read, h'0a0 is set to expevt; when the exception occurred during a write, h'0c0 is set to expevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0100. 5. address error conditions: a. instruction fetch from odd address (4n + 1, 4n + 3) b. word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) c. longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) d. virtual space accessed in user mode in the area h'8000 0000 to h'ffffffff.
105 operations: the virtual address (32 bits) that caused the exception is set to the tea. the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. when the exception occurred during a read, h'0e0 is set to expevt; when the exception occurred during a write, h'100 is set to expevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0100. see 4.5.5, processing when mmu exception occurs, in section 4, the mmu. 6. unconditional trap conditions: trapa instruction executed operations: the exception is a processing-completion type, so the pc of the instruction after the trapa instruction is saved to the spc. the sr from the time when the trapa instruction was executing is saved to the ssr. the 8-bit immediate value in the trapa instruction is quadrupled and set to tra(9?). h'160 is set to expevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0100. 7. fpu exception conditions: an fpu exception trap occurs when ev or ez in the enable field of the fpscr register is set. this indicates that a floating point computation instruction causes an invalid- operation or divide-by-zero exception as defined in ieee 754. a floating point computation instruction is one of the following: fadd, fsub, fmul, fdiv, fmac, fcmp/eq, fcmp/gt, fneg, fabs, fsqrt, or ftrc. operations: an fpu exception will only take place if the corresponding enable bit is set. when the fpu detects an exception cause, it aborts the fpu operation and signals the cpu that a trap is pending. the cpu saves the address of the offending fp opcode in the spc register, and saves the current state of the sr register in the ssr register. the bl, md, and rb bits of the sr register are set to 1 and the pc is set to vbr + h'0120. if the fpu operation was in a delay slot, the saved pc (spc) register will contain the address of the delayed branch instruction. the fpscr sticky bits will always be updated whether or not an fpu exception was taken, and will remain set until explicitly cleared by user code. the fpscr cause bits change as fp operations are executed. other exceptions defined in ieee 754, that is, underflow, overflow, and inexact exceptions, are observed by the fpu but do not cause any exception. no other data transfer floating point instructions, such as float, cause fpu exceptions. 8. general illegal instruction conditions: a. when an undefined instruction not in a delay slot is decoded
106 delay slot instructions are jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, and bf/s. undefined instructions are h'fxxf. b. when a privileged instruction not in a delay slot is decoded in user mode privileged instructions are ldc, stc, rte, ldtlb, and sleep. instructions that access gbr with ldc/stc are not privileged instructions. operations: the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. h'180 is set to expevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0100. when undefined code other than h'fxxf is decoded, operation cannot be guaranteed. 9. illegal slot instruction conditions: a. when an undefined instruction in a delay slot is decoded delay slot instructions are jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, and bf/s. undefined instructions are h'fxxf. b. when an instruction that rewrites a pc in a delay slot is decoded instructions that rewrite the pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm, sr, ldc.l, @rm+, sr c. when a privileged instruction in a delay slot is decoded in user mode privileged instructions: ldc, stc, rte, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions operations: the pc of the previous delay branch instruction is saved to the spc. the sr of the instruction that generated the exception is saved to the ssr. h'1a0 is set to expevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0100. when undefined code other than h'fxxf is decoded, operation cannot be guaranteed. 10. user break point trap conditions: when a break condition set in the user break point controller is satisfied operations: when the after-execution break occurs, the pc of the instruction immediately after the instruction that set the break point is set to the spc. if the before-execution break occurs, the pc of the instruction that set the break point is set to the spc. the sr when the break occurs is set to the ssr. h'1e0 is set to expevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0100. see section 8, user break controller, for more information.
107 5.5.3 interrupts 1. nmi conditions: nmi pin edge detected operations: the pc and sr after the instruction that receives the interrupt are saved to the spc and ssr, respectively. h'01c0 is set to intevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0600. this interrupt is not masked by sr.imask and received with top priority when the sr? bl bit is 0. when the bl bit is 1, the interrupt is masked. see section 7, interrupt controller, for more information. 2. irl pin interrupts conditions: sr.imask is lower than the irl3?rl0 level and the sr? bl bit is 0. the interrupt is accepted at an instruction boundary. operations: the pc after the instruction that accepts the interrupt is saved to the spc. the sr at the point the interrupt is accepted is saved to the ssr. the code corresponding to the irl3 to irl0 level is set to intevt. the corresponding code is shown in table 7.4, interrupt exception vectors and rankings. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to vbr + h'0600. the received level is not set to sr.imask. see section 7, interrupt controller, for more information. 3. on-chip module interrupts conditions: sr.imask is lower than the on-chip module (tmu, rtc, sci, cpg, ref) interrupt level and the sr? bl bit is 0. the interrupt is accepted at an instruction boundary. operations: the pc after the instruction that accepts the interrupt is saved to the spc. the sr at the point the interrupt is accepted is saved to the ssr. the code corresponding to the interrupt cause is set to intevt. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to vbr + h'0600. b'0000 to b'1111 are set to the interrupt priority level registers (irpa, irpb) within the interrupt controller. see section 7, interrupt controller, for more information. 5.6 cautions 1. return from exception processing a. check the sr? bl bit with software. when the spc and ssr have been saved to external memory, set the sr? bl bit to 1 before restoring them. b. issue an rte instruction. set the spc to the pc and the ssr to the sr with the rte instruction, branch to the spc address, and return from exception processing.
108 2. operation when exception or interrupt occurs while sr.bl = 1 a. interrupt suppress reception until the bl bit of the sr is set to 0 by software. if there is a request and the reception conditions are satisfied, the interrupt is received after the execution of the instruction that sets the sr? bl bit to 0. during the sleep or standby mode, however, the interrupt will be received even when the sr? bl bit is 1. b. exception no user break point trap will occur even when the break conditions are met. when one of the other exceptions occurs, it branches to the fixed address of the reset (h'a0000000). the expevt, spc, and ssr registers and the sr register? rb bit become undefined. 3. spc when an exception occurs the pc saved to the spc when an exception occurs is as shown below. a. re-executing-type exceptions the pc of the instruction that caused the exception is set to the spc and re-executed after return from exception processing. when the exception occurred in a delay slot, however, the pc of the immediately prior delay branch instruction is set to the spc. when the condition of a conditional delayed branch instruction is not met, the delayed slot pc is set to the spc. b. completed-type exceptions and interrupts the pc of the instruction after the one that caused the exception is set to the spc. when the exception occurs in a conditional delayed branch instruction, the pc at the end of the branch is set to the spc. when the condition of a conditional delayed branch instruction is not met, the delayed slot pc is set to the spc. 4. initial register values after reset undefined registers: r0_bank0/bank1?7_bank0/bank1, r8?15, gbr, spc, ssr, mach, macl, pr initialized registers: vbr=h'00000000 sr.md = 1, sr.bl = 1, sr.rb = 1, sr.i3?0 = h'f, other sr bits are undefined pc = h'a0000000 5. do not create exceptions in the delay slots of rte instructions. operation cannot be guaranteed if they occur. 6. when the sr register? bl bit is 1, do not cause a tlb related exception or address error in an instruction that updates the sr register or the instruction after that with an ldc instruction. it will be considered a multiplexed exception and reset processing will start up.
109 section 6 cache 6.1 overview 6.1.1 features the cache specifications are listed in table 6.1. table 6.1 cache specifications parameter specification capacity selectable: normal mode: 8 kbytes ram mode: 4-kbyte cache and 4-kbyte ram structure instruction/data mixed, 4-way set associative (2-way set associative in ram mode) line size 16 bytes number of entries 128 entries/way write system p0, p1, p3, u0: write-back/write-through, selectable replacement method least-recently-used (lru) algorithm 6.1.2 cache structure the cache mixes data and instructions and uses a 4-way set associative system. it is composed of four ways (banks), each of which is divided into an address section and a data section. each of the address and data sections is divided into 128 entries. the data section of the entry is called a line. each line is 16 bytes (4 bytes 4). the data capacity per way is 2 kbytes (16 bytes 128 entries), with a total of 8 kbytes in the cache as a whole (4 ways). figure 6.1 shows the cache structure.
110 entry 0 address array (ways 0?) v u tag address 24 (1 + 1 + 22) bits entry 1 entry 127 0 data array (ways 0?) lru section lw0 lw1 lw2 lw3 128 (32 4) bits lw0?w3: longword data 0? 1 127 0 1 127 6 bits figure 6.1 cache structure address array: the v bit indicates whether the entry data is valid. when the v bit is 1, data is valid; when 0, data is not valid. the u bit indicates whether the entry has been written to in write- back mode. when the u bit is 1, the entry had been written to; when 0, it has not. the tag address holds the physical address used in the external memory access. it is composed of 22 bits (addresses 31?0) used for comparison during cache searches. in the sh7718r, the top three bits of the 32-bit physical address are used as a shadow (see section 11, bus state controller), so 0 is usually entered in the top three bits of the tag address. the v and u bits are initialized to 0 by a power-on reset but not by a manual reset. the tag address is not initialized by either reset. data array: holds a 16-byte instruction or data. entries are registered in the cache in line units (16 bytes). the data array is not initialized by either a power-on reset or manual reset. lru: with the 4-way set associative system, up to four instructions or data with the same entry address (addresses 10?) can be registered in the cache. when an entry is registered, the lru bits shows which of the four ways it is recorded in. there are six lru bits; they are controlled by hardware. the least-recently-used (lru) algorithm is used to select the way. in normal mode, four ways are used as cache and six lru bits indicate the way to be replaced (table 6.2). when a bit pattern other than those listed in table 6.2 is set to the lru bits by software, the cache does not function correctly. when modifying the lru bits by software, set one of the patterns listed in table 6.2.
111 in ram mode, two ways are used as cache (way 0 and way 1). bit 5 of the lru bits indicates which way to be replaced. when bit 5 is equal to 0, way 1 is to be replaced. when bit 5 is equal to 0, way 0 is to be replaced. the lru bits are initialized to 0 by a power-on reset but are not initialized by a manual reset. table 6.2 lru bits and way replacement in normal mode lru bits (5?) way to be replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 6.1.3 register configuration table 6.3 lists the configuration of the cache control register. table 6.3 register configuration register abbr. r/w size initial value* address cache control register ccr r/w longword h'00000000 h'ffffffec note: initialized by a power-on reset or manual reset. 6.2 register description 6.2.1 cache control register (ccr) the cache is enabled or disabled using the ce bit of the cache control register (ccr). the ccr also has an ra bit (indicates the cache operation mode, ram mode or normal mode), a cf bit (invalidates all cache entries), and a wt bit (selects either write-through mode or write-back mode). programs that change the contents of the ccr register should be placed in address space that is not cached. when updating the contents of the ccr register, always set bit 4 to 0. figure 6.2 shows the configuration of the ccr register.
112 0cf wtce 4 ra ... ... ... ... ... ... ... ... ... 5 6 31 ram bit. indicates the cache operation mode. 1 = 4 kbytes cache/4 kbytes cache (ram mode) 0 = 8 kbytes cache (normal mode) always set to 0 when setting the register. cache flush bit. invalidates all cache entries. 1 = flush (clears the v, u, and lru bits of all entries to 0). always reads 0. write-back to external memory is not performed when the cache is flushed. reserved bits. always read 0; and the write value should always be 0. p1 area write-back/write-through switching bit 1 = write-back mode, 0 = write-through mode write-through bit. indicates the cache s operating mode for areas p0, u0, and p3. 1 = write-through mode, 0 = write-back mode. cache enable bit. indicates whether the cache function is used. 1 = cache used, 0 = cache not used. ra: 0: cf: : cb: wt: ce: 3210 cb figure 6.2 ccr configuration 6.3 cache operation 6.3.1 searching the cache if the cache is enabled, whenever instructions or data in memory are accessed, the cache will be searched to see if the desired instruction or data is in the cache. figure 6.3 shows the method by which the cache is searched. the cache is a physical cache and holds physical addresses in its address section. entries are selected using bits 10? of the address (virtual) of the access to memory and the tag address of that entry is read. in parallel to tag address reading, the virtual address is translated to a physical address in the mmu. the physical address after translation and the physical address (tag address) read from the address are compared. the address comparison uses all four ways in normal mode. in ram mode, two ways are used in the address comparison. when the comparison shows a match and the selected entry is valid (v = 1), a cache hit occurs. otherwise, a cache miss occurs. figure 6.3 shows a hit on way 1.
113 cmp1 0 ways 0 3 longword (lw) selection entry selection 10 3 1 40 2 31 virtual address v u tag address mmu 1 127 cmp0 hit signal 1 cmp2 cmp3 physical address ways 0 3 lw0 lw1 lw2 lw3 cmp0: cmp1: cmp2: cmp3: comparison circuit 0 comparison circuit 1 comparison circuit 2 comparison circuit 3 figure 6.3 cache search scheme (normal mode) 6.3.2 read access read hit: in a read access, instructions and data are transferred from the cache to the cpu. the transfer unit is 32 bits. the lru is updated. read miss: the external bus cycle starts up and the entry is updated. the way replaced is the one least recently used. entries are updated in 16-byte units. when the desired instruction or data is
114 loaded from external memory to the cache, the instruction or data is transferred to the cpu in parallel with being loaded to the cache. when it is loaded in the cache, the u bit is set to 0 and the v bit to 1. when the u bit of a replaced entry in the write-back mode is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer. after the cache completes its fill cycle, the write-back buffer writes back the entry to memory. the write-back unit is 16 bytes. 6.3.3 write access write hit: in a write access in the write-back mode, data is written to the cache and the u bit of the entry written is set to 1. writing occurs only to the cache; no write cycle is issued to external memory. in the write-through mode, data is written to the cache and a write cycle is issued to external memory. write miss: in the write-back mode, an external bus cycle starts up when a write miss occurs and an entry with its u bit set to a logic one is replaced. the way to be replaced is the one least recently used. when the u bit of the entry to be replaced is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer. the write-back unit is 16 bytes. data is written to the cache and the u bit is set to 1. after the cache completes its fill cycle, the write-back buffer writes back the entry to memory. in the write-through mode, no write to cache occurs in a write miss; the write is only to external memory. 6.3.4 write-back buffer when the u bit of the entry to be replaced in the write-back mode is 1, it must be written back to external memory. to increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to external memory. after new entries are fetched to the cache, the write-back buffer is written back to external memory. during the write back cycles, the cache can be accessed. the write-back buffer can hold 1 line of cache data (16 bytes) and its physical address. figure 6.4 shows the configuration of the write-back buffer. longword 0 longword 1 longword 2 longword 3 pa(31 4) pa(31 4): longword 0 3: physical address written to external memory. the line of cache data to be written to external memory. figure 6.4 write-back buffer configuration
115 6.3.5 coherency of cache and external memory use software to ensure coherency between the cache and the external memory. when memory shared by the sh7718r and another device is accessed, the latest data may be in a write-back mode cache, so invalidate the entry that includes the latest data in the cache to generate a write back and update the data in memory before using it. when the caching area is updated by a device other than the sh7718r, invalidate the entry that includes the updated data in the cache. 6.3.6 ram mode in ram mode, way 0 and way 1 function as a 4 kbytes two-way set associative cache, while way 2 and way 3 function as a 4 kbytes internal ram. instructions and data can be placed in on-chip ram and accessed in byte, word, or longword. the internal ram is mapped from h'7f000000 to h'7f000fff with 4 kbytes shadow areas from h'7f001000 to h'7fffffff. in ram mode with the mmu enabled, access of virtual addresses from h'7f000000 to h'7fffffff access on-chip ram without address translation. physical addresses cannot be mapped to on-chip ram after addresses are translated using the tlb. the internal ram can be accessed in both privileged and user mode. before changing the ra bit, all entries in the cache should be invalidated. 6.4 memory-mapped cache to allow software management of the cache, in the privileged mode, the cache contents can be read or written using the mov instruction. the cache is mapped to virtual address space p4. the address array is mapped to addresses h'f0000000 to h'f0ffffff and the data array to addresses h'f1000000 to h'f1ffffff. access size is fixed to longword for both the address and data array and instructions cannot be fetched. 6.4.1 address array the address array is mapped from h'f0000000 to h'f0ffffff. to access an address array, the 32-bit address section (for read/write) and 32-bit data section (for write) must be specified. the address section specifies information for selecting the entry to be accessed; the data section specifies the address, v bit, u bit, and lru bits to be written to the address array (figure 6.5). in the address section, specify the entry address for selecting the entry (bits 10?), the w for selecting the way (bits 12?1), and h'f0 to indicate address array access (bits 31?4). 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3 in normal mode (8 kbytes cache); 00 and 10 are way 0, and 01 and 11 are way 1 in ram mode. when writing, specify bit 3 as the a bit. the a bit indicates whether addresses are compared during writing. when the a bit is 1, the addresses of the four entries selected by the entry addresses are compared to the addresses to be written into the address array specified in the data section. writing takes place to the way that has a hit. the way number specified in bits 12?1 is
116 not used. when a miss occurs, nothing is written to the address array and no operation occurs. when the a bit is 0, it is written to the entry selected with the entry address and way number without comparing addresses. an address specified in bits 31?0 (in the (1?) data specification of figure 6.5, address array access) is a virtual address. when the mmu is enabled, the address is translated into a physical address, then the physical address is used in comparing addresses when the a bit is equal to a logic one. the physical address is written into the address array. when reading, the address tag, v bit, u bit, and lru bits of the entry specified by the entry address and way number are read in the format of the data section in figure 6.5 without comparing addresses. to invalidate a specific entry, specify the entry by entry address and w and write 0 to its v bit. when the a bit is set to a logic one, only the hit entry will be invalidated. when an entry to be invalidated by its v bit being set to a logic zero has a u bit of 1, the entry is written back. this allows coherency to be achieved between the external memory and cache by invalidating the entry. when writing 0 to the v bit, be sure to also write 0 to the entry? u bit. in the sh7718r, the top three bits of the 32-bit physical address are used as a shadow (see section 11, bus state controller), so when a cache miss occurs, 0 is registered in the top three bits of the tag address. do not set a value other than 0 to the top three bits of the tag address when changing the address array directly using the mov instruction. 6.4.2 data array the data array is mapped to h'f1000000 to h'f1ffffff. to access a data array, the 32-bit address section (for read/write) and 32-bit data section (for write) must be specified. the address section specifies information for selecting the entry to be accessed; the data section specifies the longword data to be written to the data array (figure 6.5). in the address section, specify the entry address for selecting the entry (bits 10?), the l for indicating the longword position within the (16 byte) line (bits 3?: 00 is longword 0, 01 is longword 1, 10 is longword 2, 11 is longword 3), the w for selecting the way (bits 12?1: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3 in normal mode; 00 and 10 are way 0, and 01 and 11 are way 1 in ram mode), and h'f1 to indicate data array access (bits 31?4). both reading and writing use the longword of the data array specified by the entry address, way number and longword address. the access size of the data array is fixed at longword.
117 w ***** * **** * *** * 4 entry 1111 0000 31 read access 23 24 3 0 12 13 10 11 wa 4 entry 1111 0000 31 write access address line 23 24 3 2 0 12 13 10 11 wl 4 entry 1111 0001 31 23 24 3 2 1 0 12 13 10 11 xx u v 4 lru tag address (31 10) 31 data line (both read and write) 3210 10 9 data array access (both read and write) address line address array access longword 31 0 data line x: * : 0 for read, don t care bit for write don t care bit ......... ......... ......... figure 6.5 specifying address and data for memory-mapped cache access
118 6.4.3 examples invalidating specific entries: specific cache entries can be invalidated by writing 0 to the entry? v bit. when the a bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and data is written when a match is found. if no match is found, there is no operation. r0 specifies the write data in r0 and r1 specifies the address. when the v bit of an entry in the address array is set to 0, the entry is written back if the entry? u bit is 1. ;r0 = h'01100010; vpn = b'0000 0001 0001 0000 0000 00, u = 0, v = 0 ;r1 = h'f0000088; address array access, entry = b'0001000, a = 1 ; mov.l r0,@r1 reading the data of a specific entry: this example reads the data section of a specific cache entry. the longword indicated in the data section of the data array in figure 6.5 is read to the register. r0 specifies the address and r1 is read. ;r1 = h'f100 004c; data array access, entry = b'0000100 ;way = 0, longword address = 3 ; mov.l @r0,r1 ;longword 3 is read.
119 section 7 interrupt controller (intc) 7.1 overview the interrupt controller (intc) ascertains the priority of interrupt causes and controls interrupt requests to the cpu. the intc registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 7.1.1 features intc has the following features: ? fifteen levels of interrupt priority: by setting the two interrupt-priority registers, the priorities of on-chip peripheral module interrupts can be selected from 15 levels for different request sources. ? nmi noise canceling function: the nmi input-level bit indicates the nmi pin status. by reading this bit in the interrupt exception service routine, the pin status can be checked, enabling it to cancel noise. ? external device interrupt notification ( irqout ): for example, when the sh7718r has released the bus right, the external bus master can be notified that an external interrupt, an on- chip peripheral module interrupt, or a memory refresh request has occurred, enabling the sh7718r to request the bus right.
120 7.1.2 block diagram figure 7.1 is a block diagram of the intc. ref wdt sci rtc tmu icr input control com- parator priority identifier 3 44 interrupt request ipra, iprb irl3 irl0 nmi irqout timer unit realtime clock unit serial communication interface watch dog timer memory refresh controller section of the bus state controller interrupt control register registers a, b for setting the interrupt priority levels status register tmu: rtc: sci: wdt: ref: icr: ipra, iprb: sr: (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request/ refresh request) ipr cpu internal bus bus interface intc 2 1 0 sr figure 7.1 intc block diagram
121 7.1.3 pin configuration table 7.1 lists the intc pin configuration. table 7.1 pin configuration name abbreviation i/o description nonmaskable interrupt input pin nmi i input of nonmaskable interrupt request signal interrupt input pins irl3 irl0 i input of interrupt request signals, which is maskable by sr.i3?0 bus request output pin irqout o output of signal that notifies external devices that an interrupt cause or memory refresh has occurred 7.1.4 register configuration the intc has the three registers listed in table 7.2. table 7.2 register configuration name abbr. r/w initial value* 1 address access size interrupt control register icr r/w * 2 h'fffffee0 16 interrupt priority setting register a ipra r/w h'0000 h'fffffee2 16 interrupt priority setting register b iprb r/w h'0000 h'fffffee4 16 notes: 1. initialized by a power-on reset or manual reset. 2. h'8000 when the nmi pin is at high level. h'0000 when the nmi pin is at low level. 7.2 interrupt causes there are three types of interrupt causes: nmi, irl, and on-chip peripheral modules. each interrupt has priority levels (0?6) with 1 the lowest and 16 the highest. priority level 0 masks an interrupt so its requests are ignored.
122 7.2.1 nmi interrupts the nmi interrupt has the highest priority level of 16. it is always accepted unless the bl bit of the status register in the cpu is set to 1. in sleep or standby mode, the interrupt is accepted regardless of the bl. input from the nmi pin is edge-detected. the nmi edge select bit (nmie) in the interrupt control register (icr) is used to select either the rising or falling edge. when the nmie bit of the icr register is changed, the nmi detection flag is cleared to avoid a false detection of the nmi interrupt. for this reason, the nmi interrupt is not detected for up to 20 cycles after changing the icr.nmie bit. nmi interrupt exception processing does not affect the interrupt mask level bits (i3?0) in the status register (sr). 7.2.2 irl interrupts irl interrupts are entered as levels through the irl3 irl0 pins. sh7718r irl3 irl0 irl3 irl0 figure 7.2 example of irl interrupt connections priorities are input as levels through pins irl3 irl0 . irl3 irl0 level 0 (0000) is the highest priority interrupt request (level 15); 15 (1111) indicates there is no interrupt request (level 0).
123 table 7.3 irl3 irl0 terminals and interrupt levels irl3 irl2 irl1 irl0 interrupt level remarks 0 0 0 0 15 level 15 interrupt request 0 0 0 1 14 level 14 interrupt request 0 0 1 0 13 level 13 interrupt request 0 0 1 1 12 level 12 interrupt request 0 1 0 0 11 level 11 interrupt request 0 1 0 1 10 level 10 interrupt request 0 1 1 0 9 level 9 interrupt request 0 1 1 1 8 level 8 interrupt request 1 0 0 0 7 level 7 interrupt request 1 0 0 1 6 level 6 interrupt request 1 0 1 0 5 level 5 interrupt request 1 0 1 1 4 level 4 interrupt request 1 1 0 0 3 level 3 interrupt request 1 1 0 1 2 level 2 interrupt request 1 1 1 0 1 level 1 interrupt request 1 1 1 1 0 no interrupt request irl interrupt detection has a built-in noise canceler utility. levels are sampled at every peripheral module cycle. if they remain unchanged for two cycles, noise canceling starts. this prevents the wrong level from being fetched when the irl pin changes. during standby mode, the peripheral module clock is stopped, so the 32.768 khz clock for the rtc is used instead for noise canceling. when the rtc is not used, therefore, irl interrupts cannot be used in standby mode. the priority level of the irl interrupt must not be lowered until the interrupt is accepted and the interrupt processing starts. the priority level can be changed to a higher one at any time. the interrupt mask bits (i3?0) of the status register (sr) are not affected by irl interrupt processing. 7.2.3 on-chip peripheral module interrupts on-chip peripheral module interrupts are generated by the following five modules: ? timer unit (tmu) ? real-time clock (rtc) ? serial communication interface (sci)
124 ? bus state controller (bsc) ? watchdog timer (wdt) not every interrupt cause is assigned a different interrupt vector. sources are reflected on the interrupt event register (intevt). it is easy to identify sources by using the values of the intevt register as branch offsets (in the exception service routine). the priority level (from 0?5) can be set for each module by writing to the interrupt priority setting registers a? (ipra?prb). the interrupt mask bits (i3?0) of the status register are not affected by the on-chip peripheral module interrupt processing. update the interrupt cause flag and interrupt enable flag of the on-chip peripheral modules when the bl bit of the sr is set to 1. to avoid accepting the wrong interrupt because an interrupt cause that should have been updated was not, read the on-chip peripheral module that includes the flag, then set the bl bit to 0. this ensures the necessary timing internally. to update multiple flags, simply read the register that includes the flags after the last flag is updated. to update a flag while the bl bit is 0, jump to an interrupt processing routine with an intevt register value of 0. this starts up interrupt processing along timing that recognizes the relationship between flag updating and the interrupt request within the sh7718r. in such cases, execute the rte instruction to continue processing thereafter. 7.2.4 interrupt exception processing and priority table 7.4 lists the codes for the interrupt event register (intevt) and interrupt causes, and the order of interrupt priority. each interrupt cause is assigned a unique intevt code. the start address of the interrupt service routine is common to each interrupt cause. this is why, for instance, the value of intevt is used as offset at the start of the interrupt service routine and branched to identify the interrupt cause. the order of priority of the on-chip peripheral module is set within the priority levels 0?5 at will by using the interrupt priority level set in registers a and b (ipra, iprb). the order of priority of the on-chip peripheral module is set to zero by reset. when the order of priorities for multiple interrupt causes are set to the same level and such interrupts are generated at the same time, they are processed according to the default order listed in table 7.4.
125 update interrupt priority setting registers a and b with the bl bit of the status register (sr) at 1. to prevent interrupts from being accepted by mistake, read the interrupt priority setting register and then set the bl bit to 0. this preserves the required internal timing.
126 table 7.4 interrupt exception vectors and rankings interrupt cause intevt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 16 high irl irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = irl3 irl0 = tmu0 tuni0 h'400 0 15 (0) ipra (15 12) tmu1 tuni1 h'420 ipra (11 8) tmu2 tuni2 h'440 ipra (7 4) high ticpi2 h'460 low low
127 table 7.4 interrupt exception vectors and rankings (cont) interrupt cause intevt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority rtc ati h'480 0 15 (0) ipra (3 0) high high pri h'4a0 cui h'4c0 low sci eri h'4e0 iprb (7 4) high rxi h'500 txi h'520 tei h'540 low wdt iti h'560 iprb (15 12) ref rcmi h'580 iprb (11 8) high rovi h'5a0 low low notes: tuni0 tuni2: under flow interrupts ticpi2: input capture interrupt ati: alarm interrupt pri: periodic interrupt cui: carry-up interrupt eri: receive error interrupt rxi: receive-data-full interrupt txi: transmit-data-empty interrupt tei: transmit-data-end interrupt iti: interval timer interrupt rcmi: compare match interrupt rovi: refresh counter overflow interrupt
128 7.3 register descriptions 7.3.1 interrupt priority registers a and b (ipra, iprb) interrupt priority registers a and b (ipra and iprb) are 16-bit read/write registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. a reset initializes ipra to iprb to h'0000. they are not initialized in the standby mode. bit: 15 14 13 12 11 10 9 8 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 7.5 lists the relationship between the interrupt causes and the ipra and iprb bits. table 7.5 interrupt request sources and ipra, iprb register bits 15 to 12 bits 11 to 8 bits 7 to 4 bits 3 to 0 ipra tmu0 tmu1 tmu2 rtc iprb wdt ref* 1 sci reserved * 2 notes: 1. ref is the memory refresh control unit in the bus state controller. see section 11, bus state controller, for details. 2. reserved bits: always read as 0. the write value should always be 0. as listed in table 7.5, four sets of on-chip peripheral modules are assigned to each register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from h'0 (0000) to h'f (1111). setting h'0 means priority level 0 (masking is requested); h'f is priority level 15 (the highest level). a reset initializes ipra?prb to h'0000.
129 7.3.2 interrupt control register (icr) the icr is a 16-bit register that sets the input signal detection mode of the external interrupt input pin nmi and indicates the input signal level to the nmi pin. the icr is initialized by a power-on reset or manual reset. it is not initialized in the standby mode. bit: 15 14 13 12 11 10 9 8 bit name: nmil nmie initial value: 0/1* 0 0 0 0 0 0 0 r/w: r/w r r r r r r r/w bit: 7 6 5 4 3 2 1 0 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r note: when nmi input is high: 1; when nmi input is low: 0. bit 15?mi input level (nmil): sets the level of the signal input at the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. bit 15: nmil description 0 nmi input level is low 1 nmi input level is high bit 8?mi edge select (nmie): selects whether the falling or rising edge of the interrupt request signal to the nmi is detected. bit 8: nmie description 0 interrupt request is detected on the falling edge of nmi input (initial value) 1 interrupt request is detected on rising edge of nmi input bits 14? and 7??eserved: always read as 0. the write value should always be 0.
130 7.4 operation 7.4.1 interrupt sequence the sequence of interrupt operations is explained below. figure 7.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers a and b (ipra and iprb). lower priority interrupts are held pending. if two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority (as indicated in table 7.4) is selected. 3. the priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bit (i3?0) of the status register (sr) of the cpu. if the request priority level is higher than the level in bits i3?0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. the irqout pin outputs low. 4. the cpu receives interrupts at breaks in instructions. 5. the interrupt cause code is set to the interrupt event register (intevt). 6. the status register (sr) and program counter (pc) are saved to ssr and spc, respectively. 7. the block bit (bl), mode bit (md), and register bank bit (rb) in the sr are set to 1. 8. the cpu jumps to the leading address of the interrupt service routine (the sum of h'00000600 and the value set in the vector base register (vbr)). this jump is not a delay branch. the interrupt service routine may branch with the intevt register value as its offset in order to identify the interrupt cause. this enables it to branch to the processing routine for the individual interrupt cause. notes: 1. the interrupt mask bits i3?0 in the status register (sr) are not changed by the acceptance of an interrupt in the sh7718r. 2. irqout outputs at low level until the interrupt request is cleared. when masking an interrupt cause with the interrupt mask bit, however, the irqout pin returns to high. output ignores the bl bit. 3. the interrupt cause flag should be cleared in the interrupt handler. to prevent an interrupt cause that should have been cleared from being re-accepted by mistake, read the cause flag after clearing, wait the length of time stated as the priority evaluation and sr mask bit comparison time in table 7.6, then either clear the bl bit or run an rte instruction.
131 program execution state no yes no yes no yes no no yes yes no yes no no yes no yes irqout i0 level 13 or lower? i3 i0 level 0? yes level 15 interrupt? i3 i0* level 14 or lower? note: i3 i0: interrrupt mask bits of status register (sr) figure 7.3 interrupt operation flowchart
132 7.4.2 multiple interrupts when handling multiple interrupts, an interrupt handler should include the following procedures: 1. branch to a specific interrupt handler corresponding to an interrupt cause with the code in the intevt used as a branch-offset for branching to the specific handler. 2. clear the cause of the interrupt in each specific handler. 3. save the ssr and spc to memory. 4. clear the bl bit of the sr, and set the accepted interrupt level to the imask of the sr. 5. handle the interrupt. 6. execute the rtc to complete the handler. when these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing the bl in step 4. this shortens interrupt response time for more urgent processing. 7.5 interrupt response table 7.6 shows the time from the occurrence of an interrupt request to interrupt exception processing and the start of the fetch of the starting instruction of the exception service routine (the interrupt response time). figure 7.4 shows the pipeline operation when an irl interrupt is accepted. when the sr.bl bit is 1, interrupt exception processing is masked and waits until an instruction that sets the bl bit to 0 is completed.
133 table 7.6 interrupt response time number of cycles item nmi irl peripheral module comments priority evaluation and sr mask bit comparison time 0.5 1. when bl is set to 1 by instruction execution or an exception, however, it waits until an instruction that sets bl to 0 ends. when an instruction that masks interrupt exception processing follows, it may wait longer. time from interrupt exception processing (saving of sr and pc) to start of fetch of starting instruction in exception service routine 5 0.14 ? max* 3 7 + s 13 + s 10.5 + s at 60 mhz: 0.23 0.34 ? (when operand is cache hit) at 60 mhz: 0.27 0.37 ? (when external memory access has a wait = 0) notes: 1. abbreviations: icyc: time for 1 cycle of internal clock supplied to cpu, etc. bcyc: time for 1 ckio cycle pcyc: time for 1 cycle of peripheral clock supplied to peripheral modules
134 2. s includes memory access waiting time. the process that takes the longest is ldc.l @rm+,sr, which takes 7 instruction execution cycles when the memory access hits the cache. when an external access is performed, those cycles must be added on. some instructions access external memory twice, so when external memory access is slow, the number of instruction execution cycles increases accordingly. 3. the internal clock: ckio: peripheral clock ratio is 1:1:1. 4. the internal clock: ckio: peripheral clock ratio is 1:1:1/4. irl if if id ex if id ex ex ex ex 0.5 figure 7.4 example of pipeline operation when irl interrupt is accepted
135 section 8 user break controller (ubc) 8.1 overview the user break controller (ubc) provides functions that simplify program debugging. this function makes it easy to design a self-monitoring debugger, enabling the chip to debug programs simply without using an in-circuit emulator. the break conditions that can be set in the ubc are instruction fetch data, read/write, data size, data content, address value, and halt timing at time of instruction fetch. 8.1.1 features the features of the user break controller are listed below. ? two break channels (channel a, channel b). user break interrupts can be requested using either independent or sequential condition for the two channels (sequential breaks are channel a, then channel b). ? the following break compare conditions can be selected and set: ? address (select what will be compared to the 32-bit virtual address and asid) ? address: compare all bits, mask bottom 10 bits, mask bottom 12 bits, mask all bits ? asid: compare all bits, mask all bits data (channel b only, 32 bits maskable) bus cycle: instruction fetch/data access read or write operand size: byte/word/longword ? select either to break in the instruction fetch cycle before the instruction is executed or after. ? user break trap generated upon satisfying break conditions. a user-designed user break interrupt exception processing routine can be run. 8.1.2 block diagram figure 8.1 shows the block diagram of the user break controller.
136 bbra address comparator access comparator address comparator data comparator access comparator access control address bus channel a channel b data bus control basra bamra bara bbrb basrb bamrb barb brcr user break trap request bdrb bdmrb bbra: bara: basra: bamra: bbrb: barb: basrb: bamrb: bdrb: bdmrb: brcr: break bus cycle register a break address register a break asid register a break address mask register a break bus cycle register b break address register b break asid register b break address mask register b break data register b break data mask register b break control register figure 8.1 block diagram of user breakpoint controller
137 8.1.3 register set table 8.1 shows the register set for the user break controller. table 8.1 ubc register set chan- nel register abbr. r/w initial value* 1 access size access address a break address register a bara r/w undefined longword h'ffffffb0 break asid register a basra r/w undefined byte h'ffffffe4 break address mask register a bamra r/w undefined byte h'ffffffb4 break bus cycle register a bbra r/w h'0000* 2 word h'ffffffb8 b break address register b barb r/w undefined longword h'ffffffa0 break address mask register b bamrb r/w undefined byte h'ffffffa4 break asid register b basrb r/w undefined byte h'ffffffe8 break bus cycle register b bbrb r/w h'0000* 2 word h'ffffffa8 break data register b bdrb r/w undefined longword h'ffffff90 break data mask register b bdmrb r/w undefined longword h'ffffff94 both break control register brcr r/w h'0000* 2 word h'ffffff98 notes: 1. holds values during standby. 2. initialized by power-on reset or manual reset. 8.1.4 setting break conditions and registers break conditions and register settings are related as follows: 1. channel a or b and the respective break conditions are set in registers. 2. addresses are set in bara and barb. asids are set in the basra and basrb registers. the bama and bamb bits of the bamra and bamrb registers set whether to include addresses in the break conditions or whether to mask them. to include asids in the conditions, set the basma and basmb bits of the bamra and bamrb registers. 3. the bus cycle break conditions are set in the bbra and bbrb registers. instruction fetch or data access, read or write, and the data access size are set. for an instruction fetch, use the pcba and pcbb bits in the brcr register to set to break before or after the instruction execution. 4. for channel b, data can be included in the break conditions. set the data in the bdrb register. to mask data, set the bdmrb register. use the dbeb bit of the brcr register to set whether to include data in the break conditions.
138 5. to use channels a and b sequentially, set the seq bit in the brcr register. when set for sequential use, a user break occurs when the channel a conditions are met and then the channel b conditions are met. 6. the cmfa and cmfb bits in the brcr register are set to 1 when a user break occurs. to generate a break again, set cmfa and cmfb to 0.
139 8.2 register descriptions 8.2.1 break address registers (bara and barb) break address registers a and b (bara and barb) are 32-bit read/write registers that specify the virtual address that is the channel a or channel b break condition. they are not initialized by manual resets; instead they hold their values. bits 31 to 0?reak address a31 to a0 (baa31 to baa0), b31 to b0 (bab31 to bab0): these bits store the virtual address (bits 31 to 0) of the channel a or channel b break condition. bit: 31 30 29 28 27 26 25 24 bit name: baa31/ bab31 baa30/ bab30 baa29/ bab29 baa28/ bab28 baa27/ bab27 baa26/ bab26 baa25/ bab25 baa24/ bab24 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bit name: baa23/ bab23 baa22/ bab22 baa21/ bab21 baa20/ bab20 baa19/ bab19 baa18/ bab18 baa17/ bab17 baa16/ bab16 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bit name: baa15/ bab15 baa14/ bab14 baa13/ bab13 baa12/ bab12 baa11/ bab11 baa10/ bab10 baa9/ bab9 baa8/ bab8 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: baa7/ bab7 baa6/ bab6 baa5/ bab5 baa4/ bab4 baa3/ bab3 baa2/ bab2 baa1/ bab1 baa0/ bab0 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w 8.2.2 break address space identification registers a and b (basra and basrb) break address space identification registers a and b (basra and basrb) are 8-bit read/write registers that specify the asid for the channel a or b break condition. they are compared to the
140 asid field of the mmu? pteh register. they are not initialized by manual resets; instead they hold their values. bits 31 to 0?reak asid a7 to a0 (basa7 to basa0), b7 to b0 (basb7 to basb0): these bits store the asid (bits 7 to 0) of the channel a or channel b break condition. bit: 7 6 5 4 3 2 1 0 bit name: basa7/ basb7 basa6/ basb6 basa5/ basb5 basa4/ basb4 basa3/ basb3 basa2/ basb2 basa1/ basb1 basa0/ basb0 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w 8.2.3 break address mask register a (bamra) break address mask register a (bamra) is an 8-bit read/write registers that specifies the bits of the asid set in the basra register and the break address set in the bara register to be masked. it is not initialized by manual resets; instead they hold their values. bit: 7 6 5 4 3 2 1 0 bit name: basma bama1 bama0 initial value: 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 7??eserved: these bits are always read as 0. the write value should always be 0. bit 2?reak asid mask a (basma): specifies which bits of the channel a break asid7 to asid0 (basa7?asa0) set in basra to mask. bit 2: basma description 0 do not mask basra; include all bits in break conditions 1 mask all basra bits; do not include asid in break conditions
141 bits 1??reak address mask a1?0 (bama1?ama0): specifies which bits of the channel a break address 31? (baa31?aa0) set in bara to mask. bit 1: bama1 bit 0: bama0 description 0 0 no bara bits are masked, entire 32-bit address is included in break conditions 1 lower-order 10 bits of bara are masked 1 0 lower-order 12 bits of bara are masked 1 all bara bits are masked; address is not included in break conditions 8.2.4 break address mask register b (bamrb) the break address mask register for channel b. bit configuration is the same as bamra. 8.2.5 break bus cycle register a (bbra) break bus cycle register a (bbra) is a read/write 16-bit register that sets (1) instruction fetch/data access, (2) read/write, and (3) operand size for the channel a break conditions. it is initialized to h'0000 by power-on resets and manual resets. bit: 15 14 13 12 11 10 9 8 bbra/bbrb: initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 bbra/bbrb: ida1 ida0 rwa1 rwa0 sza1 sza0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w bits 15??eserved: these bits are always read as 0. the write value should always be 0.
142 bits 5??instruction fetch / data access a (ida1, ida0): specify instruction fetch bus cycle or data access cycle for the channel a break condition. bit 5: ida1 bit 4: ida0 description 0 0 conditions not compared (initial value) 1 break condition is instruction fetch cycle 1 0 break condition is data access cycle 1 break condition is both instruction fetch cycle and data access cycle bits 3??ead/write select a (rwa1, rwa0): specify read cycle or write cycle for the channel a break condition bus cycle. bit 3: rwa1 bit 2: rwa0 description 0 0 conditions not compared (initial value) 1 break condition is read cycle 1 0 break condition is write cycle 1 break condition is both read cycle and write cycle bits 1??perand size select a (sza1, sza0): specify operand size for the channel a break condition bus cycle. bit 1: sza1 bit 0: sza0 description 0 0 operand size not included in comparison conditions (initial value) 1 break on byte access 1 0 break on word access 1 break on longword access 8.2.6 break bus cycle register b (bbrb) the break bus condition register for channel b. bit configuration is the same as bbra.
143 8.2.7 break b data register (bdrb) the break b data register (bdrb) is a 32-bit read/write register that specifies the data (bits 31?) that is the break condition for channel b data breaks. it is not initialized by a manual reset; instead, it holds its values. bits 31??reak data b31?0 (bdb31?db0): holds the data that is the break condition for channel b data breaks (bits 31?). when the szb bit is set in the bbrb register, set the same byte data in bits bdb15?db8 as in bdb7?db0. when set for byte or word access, bits bdb31 to bdb16 are ignored. when instruction fetch is specified as a break condition for channel b or 0 is specified in the brcr? dbeb bit to not include the data bus in compared conditions, the bdrb register value is ignored. bit: 31 30 29 28 27 26 25 24 bit name: bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bit name: bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bit name: bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w
144 8.2.8 break b data mask register (bdmrb) the break b data mask register (bdmrb) is a 32-bit read/write register that provides a masking bit corresponding to each bit of bdrb. it is not initialized by a manual reset; instead, it holds its values. bit: 31 30 29 28 27 26 25 24 bit name: bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bit name: bdmb23 bdmb22 bdmb21 bdmb20 bdmb19 bdmb18 bdmb17 bdmb16 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bit name: bdmb15 bdmb14 bdmb13 bdmb12 bdmb11 bdmb10 bdmb9 bdmb8 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 31??reak data mask b31?0 (bdmb31?dmb0): specifies which bits in the channel b break data b31?0 (bdb31?db0) set in bdrb to mask. when byte is specified for size, set the same values in bdmd15?dmb8 as in bdmb7?dmb0. bits 31?: bdmbn description 0 include break data bdbn in the channel b break conditions 1 do not include break data bdbn in the channel b break conditions n = 31? cautions ? specify the operand size when data bus values are included in the break conditions.
145 ? when byte size is specified, set the same values in bits 15? and 7? of the bdrb and bdmrb registers. ? for word or byte sizes, bits 31?6 of the bdrb and bdmrb registers are ignored. 8.2.9 break control register (brcr) the break control register (brcr) is a 16-bit read/write register that controls user breaks. the brcr sets (1) whether channels a and b use independent or sequential conditions, (2) whether breaks occur before or after instruction execution, and (3) whether the bdrb register is included in the channel b break conditions. it also has condition match flags. brcr is cleared to h'0000 at a power-on reset or manual reset. bit: 15 14 13 12 11 10 9 8 bit name: cmfa cmfb pcba initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r r r r/w r r bit: 7 6 5 4 3 2 1 0 bit name: dbeb pcbb seq initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r r r/w r r r bit 15?onditions met flag a (cmfa): set to 1 when the break conditions for channel a have been met. it is not cleared to 0. to use it again after it has been set, write 0 to clear it. bit 15: cmfa description 0 channel a break conditions not met (initial value) 1 channel a break conditions met bit 14?onditions met flag b (cmfb): set to 1 when the break conditions for channel b have been met. it is not cleared to 0. to use it again after it has been set, write 0 to clear it. bit 14: cmfb description 0 channel b break conditions not met (initial value) 1 channel b break conditions met bits 13?1?eserved: these bits are always read as 0. the write value should always be 0.
146 bit 10?rogram counter break a trap (pcba): indicates if the trap for the channel a instruction fetch address break is taken before or after execution of the fetched instruction. bit 10: pcba description 0 breaks prior to execution of channel a pc break (initial value) 1 breaks after execution of channel a pc break bits 9??eserved: these bits are always read as 0. the write value should always be 0. bit 7?ata break enable bit (dbeb): indicates if the data bus is included in the channel b break conditions, as follows: bit 7: dbeb description 0 data bus conditions not included in channel b conditions (initial value) 1 data bus conditions included in channel b conditions note: to include the data bus in the break conditions, set the idb1?db0 field in the bbrb to 10 or 11. bit 6?rogram counter break select b (pcbb): indicates if the trap for the channel b instruction fetch address break is taken before or after execution of the fetched instruction. bit 6: pcbb description 0 breaks prior to execution of channel b pc break (initial value) 1 breaks after execution of channel b pc break bits 5??eserved: these bits are always read as 0. the write value should always be 0. bit 3?equential condition select (seq): indicates if the channel a and channel b break conditions are checked independently or in sequence. when set for sequential, the cmfb flag is set when channel b conditions are met after channel a conditions are met. bit 3: seq description 0 channel a and channel b are compared independently (initial value) 1 channel a and channel b are compared sequentially (channel a met before channel b) bits 2??eserved: these bits are always read as 0. the write value should always be 0.
147 8.3 operation 8.3.1 flow of the user break operation the flow from setting of break conditions to user break interrupt exception processing is described below: 1. the break addresses are set in the break address registers (bara, barb), the asids corresponding to the space for the break are set in the break asid registers (basra, basrb), and the masked addresses and asid mask method are set in the break address mask registers (bamra, bamrb). when data bus values are included in break conditions, the break data is set in the break data register (bdrb) and the masked data is set in the break data mask register (bdmrb). 2. the breaking bus conditions are set in the break bus cycle registers (bbra, bbrb). if one of the two registers bbra and bbrb is set to 00 for instruction fetch/data access and read/write, no user break trap will be generated for the channel concerned. set the break control register (brcr) to specify breaking before or after execution in the case of instruction fetch, whether to include data bus values in the case of data access, independent or sequential conditions for channels a and b. set the bbra and bbrb registers after the other break-related registers have all been set. if breaks are enabled with the bbra and bbrb registers with the registers for break address, data, masking and the like in their initial states after reset, breaks will occur in the wrong places. 3. when the set conditions are satisfied, the condition match flags (cmfa, cmfb) for the respective channels are set. once set by a break condition match, they are not reset. to use them again, set them to 0. 4. when set for sequential conditions, a break occurs at the instruction that matches the channel b conditions if the channel a conditions have been previously matched. no break occurs if the channel b conditions are matched before or simultaneous to matching the channel a conditions. the condition match flag is only set for channel b when conditions match when set for sequential matching. 8.3.2 break on instruction fetch cycle 1. when instruction fetch/read/word is set in the break bus cycle registers (bbra/bbrb), the break condition becomes the instruction fetch cycle. whether it then breaks before or after the execution of the instruction can then be selected with the pcba and pcbb bits of the break control register (brcr). 2. the instruction fetch cycle always fetches 32 consecutive bits (two instructions) at once. only one bus cycle occurs, but breaks can be placed on each instruction individually by setting the respective start addresses in the break address registers (bara, barb). 3. an instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. this means this feature cannot be used on instructions
148 fetched by overrun (instructions fetched at a branch or during an exception transition, but not to be executed). when an exception occurs when the instruction of the break is fetched, the exception is processed and then the break occurs when the instruction is re-executed. delay slot instructions and delayed branch instructions are executed as single instructions, so when break before execution is set for a delay slot instruction, the break occurs before the delay branch instruction. break before execution cannot be specified for the rte instruction? delay slot instruction. 4. when the condition stipulates after execution, the instruction set with the break condition is executed and then the break trap is generated prior to the execution of the next instruction. as with pre-execution breaks, this cannot be used with overrun fetch instructions. when this kind of break is set for a delayed branch instruction, the delay slot is executed and the break occurs before execution of the instruction at the end of the branch. 5. when an instruction fetch cycle is set for channel b, break data register b (bdrb) is ignored. there is thus no need to set break data for the break of the instruction fetch cycle. 6. instruction fetch cycle breaks cannot be set after delayed branch instructions and delay slots. 8.3.3 break on data access cycle 1. when breaks occur on data access cycles, the specification for operand size in the break bus cycle registers (bbra and bbrb) changes the bits of the address bus comparison as follows listed in table 8.2. table 8.2 breaks on data access cycles operand size address compared not included (00) compare address bits a31?0 for byte access compare address bits a31?1 for word access compare address bits a31?2 for longword access byte (01) compare address bits a31?0 word (10) compare address bits a31?1 longword (11) compare address bits a31?2 2. when the data value is included in the break conditions on channel b, set the brcr? dbeb bit to 1. in addition to address conditions, break data register b (bdrb) and break data mask register b (bdmrb) must both be set. when address and data conditions both match, a user break trap is generated. set the idb1?db0 field in the bbrb to 00 or 01. when specifying byte data, set the same data in the two bytes at bits 15? and bits 7? of the break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31?6 of bdrb and bdmrb are ignored.
149 8.3.4 program counter (pc) values saved 1. break on instruction fetch (before execution): the program counter (pc) value saved to the spc in user break interrupt processing is the address of the instruction that matches the break condition. the user break interrupt is generated before the fetched instruction. which is not executed. in fetch cycles of instructions placed in the delay slots of delayed branch instructions, the break occurs before the branch, so the spc value is the delayed branch instruction. 2. break on instruction fetch (after execution): the program counter (pc) value saved to the spc in user break interrupt processing is the address of the instruction executed after the one that matches the break condition. the fetched instruction is executed and the user break interrupt is generated before the next instruction. if a break condition is set on a delayed branch instruction, the delay slot instruction is executed and the user break occurs before the instruction at the end of the branch is executed. the pc value saved to the spc is the address of the delayed branch instruction. 3. break on data access (address only): the address of the instruction after the one that matched the conditions is saved. the instruction is executed and the user break trap occurs before execution of the next instruction. 4. break on data access (address + data): the top address of the instruction after the executed instruction when the user break trap processing started is saved. when data values are set as a break condition, the place where the break will occur cannot be specified exactly. the break will occur before execution of an instruction fetched near the data access that is to receive the break. 8.3.5 examples this section shows how register settings, already set conditions, and conditions set match. break on an instruction fetch bus cycle (channels a and b independent) brcr = h'0400: a and b channels independent, channel a after instruction execution, channel b before instruction execution.
150 channel a basra = h'80: asid h'80 bara = h'00000404: address = h'00000404 bamra = h'00: address mask h'00 bbra = h'0014: bus cycle = instruction fetch (after execution), read (operand size not included in conditions) channel b basrb = h'70: asid h'70 barb = h'00008010: address = h'00008010 bamrb = h'02: address mask h'02 bbrb = h'0014: bus cycle = instruction fetch (before execution), read (operand size not included in conditions) bdrb = h'00000000: data h'00000000 bdmrb = h'00000000: data mask h'00000000 a user break will occur after the instruction at address h'00000404 with asid=h'80 is executed, or a user break will be generated before the execution of the instruction at address h'00008000 to h'000083fe with asid=h'70. break on an instruction fetch bus cycle (channels a and b sequential) brcr = h'0008: a and b channels sequential, channel a before instruction execution, channel b before instruction execution. channel a basra = h'80: asid h'80 bara = h'00037226: address = h'00037226 bamra = h'00: address mask h'00 bbra = h'0016: bus cycle = instruction fetch (before execution), read, word channel b basrb = h'70: asid h'70 barb = h'0003722e: address = h'0003722e bamrb = h'00: address mask h'00 bbrb = h'0016: bus cycle = instruction fetch (before execution), read, word bdrb = h'00000000: data h'00000000 bdmrb = h'00000000: data mask h'00000000 the instruction at address h'00037226 with asid=h'80 will be executed and then a user break will occur before the instruction at address h'0003722e with asid=h'70 is executed.
151 break on a data access cycle brcr = h'0080: a and b channels independent, data break enabled. channel a basra = h'80: asid h'80 bara = h'00123456: address = h'00123456 bamra = h'00: address mask h'00 bbra = h'0024: bus cycle = data access, read (operand size not included in conditions) channel b basrb = h'70: asid h'70 barb = h'000abcde: address = h'000abcde bamrb = h'02: address mask h'02 bbrb = h'002a: bus cycle = data access, write, word bdrb = h'0000a512: data h'0000a512 (data break enabled) bdmrb = h'00000000: data mask h'00000000 for channel a, a user break interrupt occurs when it is read as longword at address h'00123454 with asid=h'80, as word at address h'00123456 or as byte at address h'00123456. for channel b, a user break interrupt occurs when h'a512 is written as word anywhere between h'000ab000 and h'000abffe (inclusive) with asid=h'70. break on an instruction fetch cycle (error in settings) brcr = h'0000: a and b channels independent, channel a before instruction execution, channel b before instruction execution. channel a basra = h'80: asid h'80 bara = h'00027128: address = h'00027128 bamra = h'00: address mask h'00 bbra = h'001a: bus cycle = instruction fetch (before execution), write, word channel b basrb = h'70: asid h'70 barb = h'00031415: address = h'00031415 bamrb = h'00: address mask h'00 bbrb = h'0014: bus cycle = instruction fetch (before execution), read (operand size not included in conditions) bdrb = h'00000000: data h'00000000 bdmrb = h'00000000: data mask h'00000000 a user break trap is not generated for channel a since the instruction fetch is not a write cycle. a user break is not generated for channel b because the instruction fetch is for an odd address.
152 8.3.6 cautions 1. when one channel has a break before execution set on an instruction and the other channel has a break after execution set on the same instruction, the break will occur before execution, but the condition match flags will be set for both. 2. do not set a pc break on both a delayed branch instruction and a delay slot instruction consecutively. 3. when a pc break (after execution) is set on a trapa instruction, no break will occur, though the condition match flag will be set. the trapa instruction will be processed correctly. 4. when a break condition is set on a data access (address + data) and an exception occurs on the instruction after the break conditions are matched, no break will occur, though the condition match flag will be set. the exception occurring after the break will be processed correctly. data breaks have priority, however, for delayed branch instructions. 5. when a break condition is set on a data access (address + data) and the instruction after the break conditions are matched is a sleep instruction, no break will occur, though the condition match flag will be set. the sleep instruction will be processed correctly. 6. when instruction fetch (halt after execution) is set for the break condition and the instruction after the break condition is matched detects a nonmaskable interrupt, no break will occur, though the condition match flag will be set. the nonmaskable interrupt will be processed correctly 7. when set for a sequential break, conditions match when a match of channel b conditions occurs some time after the bus cycle in which a channel a match occurs. this means that the conditions will not be satisfied when set for a bus cycle in which channel a and channel b occur simultaneously. since the cpu uses a pipeline structure, the order of the instruction fetch cycle and memory cycle is fixed by the pipeline, so sequential conditions means that the sequential conditions will be satisfied when the respective channel conditions are met in the order the bus cycles occur. 8. when the emulator is used, the ubc is used on the emulator system side to implement the emulator? break function. this means none of the ubc functions can be used when the emulator is being used.
153 section 9 power-down modes 9.1 overview in the power-down modes, all cpu and some on-chip supporting module functions are halted. this lowers power consumption. 9.1.1 power-down modes the sh7718r has three power-down modes: 1. sleep mode 2. standby mode 3. module standby function (tmu, rtc, and sci on-chip supporting modules) 4. hardware standby mode table 9.1 shows the transition conditions for entering the modes from the program execution state, as well as the cpu and supporting module states in each mode and the procedures for canceling each mode.
154 table 9.1 power-down modes state mode transition conditions cpg cpu cpu reg- ister on-chip memory on-chip peripheral modules pins external memory canceling procedure sleep mode execute sleep instruction with stby bit cleared to 0 in stbcr runs halts held held run held refresh 1. interrupt 2. reset standby mode execute sleep instruction with stby bit set to 1 in stbcr halts halts held held halts* 1 held self- refresh 1. interrupt 2. reset hardware standby mode drive ca pin low halts halts held held halts* 3 held self- refresh power-on reset module standby set mstp bit of stbcr to 1 runs runs held held specified module halts * 2 refresh 1. clear mstp bit to 0 2. reset notes: 1. the rtc still runs if the start bit in rcr2 is set to 1 (see section 12, realtime clock (rtc)). tmu still runs when output of the rtc is used as input to its counter (see section 11, timer (tmu)). 2. depends on the on-chip supporting module. tmu external pin: held sci external pin: reset 3. the rtc still runs if the start bit in rcr2 is set to 1 (see section 12, realtime clock (rtc)). the tmu does not run. 9.1.2 register configuration table 9.2 shows the configuration of the control register for the power-down modes. table 9.2 register configuration name abbreviation r/w initial value address access size standby control register stbcr r/w h'00 h'ffffff82 byte
155 9.1.3 pin configuration table 9.3 lists the pins used for the power-down modes. table 9.3 pin configuration processing status 1 pin (status1) processing status 0 pin (status0) i/o processor operating status high high o reset low sleep mode low high standby mode low normal operation 9.2 register description 9.2.1 standby control register (stbcr) the standby control register (stbcr) is an 8-bit read/write register that sets the power-down mode. stbcr is initialized to h'00 by a power-on reset. always set bits 6? to 0 when writing to the stbcr register. bit: 7 6 5 4 3 2 1 0 bit name: stby mstp2 mstp1 mstp0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r r/w r/w r/w bit 7?tandby (stby): specifies transition to standby mode. bit 7: stby description 0 executing sleep instruction puts the chip into sleep mode. (initial value) 1 executing sleep instruction puts the chip into standby mode. bits 6 to 3?eserved: these bits are always read as 0. the write value should always be 0.
156 bit 2?odule standby 2 (mstp2): specifies halting the clock supply to the timer unit tmu (an on-chip supporting module). when the mstp2 bit is set to 1, the supply of the clock to the tmu is halted. bit 2: mstp2 description 0 tmu runs. (initial value) 1 clock supply to tmu is halted. bit 1?odule standby 1 (mstp1): specifies halting the clock supply to the realtime clock rtc (an on-chip supporting module). when the mstp1 bit is set to 1, the supply of the clock to rtc is halted. when the clock halts, all rtc registers become inaccessible, but the counter keeps running. bit 1: mstp1 description 0 rtc runs. (initial value) 1 clock supply to rtc is halted. bit 0?odule standby 0 (mstp0): specifies halting the clock supply to the serial communication interface sci (an on-chip supporting module). when the mstp0 bit is set to 1, the supply of the clock to the sci is halted. bit 0: mstp0 description 0 sci operates. (initial value) 1 clock supply to sci is halted.
157 9.3 sleep mode 9.3.1 transition to sleep mode executing the sleep instruction when the stby bit in stbcr is 0 causes a transition from the program execution state to sleep mode. although the cpu halts immediately after executing the sleep instruction, the contents of its internal registers remain unchanged. the on-chip supporting modules continue to run during sleep mode and the clock continues to be output to the ckio pin. in sleep mode, the status1 pin is set high and the status0 pin low. however, during a refresh cycle, the status1 pin and status0 pin are both set low. 9.3.2 canceling sleep mode sleep mode is canceled by an interrupt (nmi, irl, on-chip supporting module) or reset. interrupts are accepted during sleep mode even when the bl bit in the sr register is 1. canceling with an interrupt: when an nmi, irl or on-chip supporting module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. a code indicating the interrupt source is set in the intevt register. canceling with a reset: sleep mode is canceled by a power-on reset or a manual reset. 9.4 standby mode 9.4.1 transition to standby mode to enter standby mode, set the stby bit to 1 in stbcr, then execute the sleep instruction. the chip moves from the program execution state to standby mode. in standby mode, power consumption is greatly reduced by halting not only the cpu, but the clock and on-chip supporting modules as well. the clock output from the ckio pin also halts. cpu and cache register contents are held, but some on-chip supporting modules are initialized. table 9.4 lists the states of registers in standby mode.
158 table 9.4 register states in standby mode module registers initialized registers retaining data interrupt controller all registers break controller all registers bus state controller all registers on-chip clock pulse generator all registers timer unit tstr register registers other than tstr realtime clock all registers the procedure for moving to standby mode is as follows: 1. clear the tme bit in the wdt? timer control register (wtcsr) to 0 to stop the wdt. set the wdt? timer counter (wtcnt) and the cks2?ks0 bits of the wtcsr register to appropriate values to secure the specified oscillation settling time. 2. when pll circuit 1 is running in clock modes 3?, clear the pstby and pllen bits in the frequency control register (frqcr) to 0 to stop pll circuit 1. 3. after the stby bit in the stbcr register is set to 1, a sleep instruction is executed. 4. standby mode is entered and the clocks within the chip are halted. the status1 pin output goes low and the status0 pin output goes high. 9.4.2 canceling standby mode standby mode is canceled by an interrupt (nmi, irl, or on-chip supporting module) or a reset. canceling with an interrupt: the on-chip wdt can be used for hot starts. when the chip detects an nmi, irl, *1 or on-chip supporting module (except the interval timer) *2 interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the wdt? timer control/status register has elapsed. the status1 and status0 pins both go low. interrupt handling then begins and a code indicating the interrupt source is set in the intevt register. interrupts are accepted during standby mode even when the bl bit in the sr register is 1. immediately after an interrupt is detected, the phase of the clock output of the ckio pin may be unstable, until the processor starts interrupt handling. (the canceling condition is that the irl3?rl0 level is higher than the mask level in the i3?0 bits in the sr register.) notes: 1. when the rtc is being used, standby mode can be canceled using irl3?rl0. 2. standby mode can be canceled with an rtc or tmu (only when running on the rtc clock) interrupt.
159 canceling with a reset: standby mode can be canceled with a reset (power-on or manual). keep the reset pin low until the clock oscillation settles. the internal clock will continue to be output to the ckio pin. 9.4.3 clock pause function in standby mode, the clock input from the extal pin or ckio pin can be halted and the frequency can be changed. this function is used as follows: 1. enter standby mode using the appropriate procedures. 2. once standby mode is entered and the clock stopped within the chip, the status1 pin output is low and the status0 pin output is high. 3. once the status1 pin goes low and the status0 pin goes high, the input clock is stopped or the frequency is changed. 4. when the frequency is changed, an nmi or irl interrupt is input after the change. when the clock is stopped, the same interrupts are input after the clock is applied. 5. after the time set in the wdt has elapsed, the clock starts being applied internally within the chip, the status1?tatus0 pins both go low, interrupts are handled, and operation resumes. 9.5 module standby function 9.5.1 transition to module standby function setting the standby control register mstp2?stp0 bits to 1 halts the supply of clocks to the corresponding on-chip supporting modules. this function can be used to reduce the power consumption in sleep mode. the module standby function holds the status prior to halt of the external pins of the on-chip supporting modules. tmu external pins hold their status prior to the halt. sci external pins go to the reset state. with a few exceptions, all registers hold their values. bit value description mstp2 0 tmu runs. 1 supply of clock to tmu is halted. registers are initialized. *1 mstp1 0 rtc runs. 1 supply of clock to rtc is halted. register access is prohibited. *2 mstp0 0 sci operates. 1 supply of clock to sci is halted. notes: 1. the registers initialized are the same as in standby mode (table 9.4). 2. the counter runs.
160 9.5.2 clearing the module standby function the module standby function can be cleared by clearing the mstp2?stp0 bits to 0, or by a power-on reset or manual reset. 9.6 timing of status pin changes the timing of status1 and status0 pin changes is shown in figures 9.1 through 9.9. the meaning of the status descriptions is as follows: reset: hh (status1 high, status0 high) sleep: hl (status1 high, status0 low) standby: lh (status1 low, status0 high) normal: ll (status1 low, status0 low) the meaning of the clock units is as follows: bcyc: bus clock cycle pcyc: peripheral clock cycle 9.6.1 timing for resets power-on reset (clock modes 0, 1, 2, and 7): ckio reset status normal normal reset pll settling time 0 to 5 bcyc 0 to 30 bcyc figure 9.1 power-on reset (clock mode 0, 1, 2, and 7) status output
161 power-on reset (clock modes 3 and 4): ckio reset status normal normal reset 0 to 5 bcyc 0 to 30 bcyc figure 9.2 power-on reset (clock mode 3 and 4) status output manual reset: ckio reset status normal normal reset 0 bcyc or more* 0 to 30 bcyc * during manual reset, status becomes hh (reset) and the internal reset begins after waiting for the executing bus cycle to end. note: figure 9.3 manual reset status output
162 9.6.2 timing for canceling standbys standby to interrupt: ckio status normal normal wdt count oscillation stops standby interrupt request wdt overflow figure 9.4 standby to interrupt status output standby to power-on reset: ckio status normal normal oscillation stops standby 0 to 10 bcyc 0 to 30 bcyc reset reset reset * 1 1. when standby mode is cleared with a power-on reset, the wdt does not count. keep reset low during the pll s oscillation settling time. * : undefined note: * figure 9.5 standby to power-on reset status output
163 standby to manual reset: ckio status normal normal oscillation stops standby reset 0 to 20 bcyc reset reset * * when standby mode is cleared with a manual reset, the wdt does not count. keep reset low during the pll s oscillation settling time. note: figure 9.6 standby to manual reset status output 9.6.3 timing for canceling sleep mode sleep to interrupt: ckio status normal normal sleep interrupt request figure 9.7 sleep to interrupt status output
164 sleep to power-on reset: ckio status normal normal sleep 0 to 10 bcyc 0 to 30 bcyc reset reset * reset * 1 1. when the pll1 s multiplication ratio is changed by a power-on reset, keep reset low during the pll s oscillation settling time. * : undefined note: figure 9.8 sleep to power-on reset status output sleep to manual reset: ckio 0 to 30 bcyc 0 to 30 bcyc reset status normal normal sleep reset reset * * keep reset low until the status becomes reset. note: figure 9.9 sleep to manual reset status output
165 9.7 hardware standby mode 9.7.1 transition to hardware standby mode driving the ca pin low causes a transition to hardware standby mode. in hardware standby mode, all modules except those operating on an rtc clock are halted, as in the standby mode entered on execution of a sleep instruction. hardware standby mode differs from standby mode as follows. 1. interrupts and manual resets are not accepted. 2. the tclk clock output is fixed low. 3. the tmu does not operate. 4. the rtc continues to operate even if power is not supplied to power supply pins other than those for rtc power. in this case, all output pins go to the non-drive state. operation when a low-level signal is input at the ca pin depends on the cpg state, as follows. 1. in standby mode the clock remains stopped and the chip enters the hardware standby state. acceptance of interrupts and manual resets is disabled, tclk output is fixed low, and the tmu halts. 2. during wdt operation when standby mode is canceled by an interrupt the chip enters hardware standby mode after standby mode is canceled and the cpu resumes operation. 3. in sleep mode the chip enters hardware standby mode after sleep mode is canceled and the cpu resumes operation. 4. during pll standby (see section 9.6 for the pll standby function) the chip enters hardware standby mode after forced implementation of the pll off state. hold the ca pin low in hardware standby mode.
166 9.7.2 canceling hardware standby mode hardware standby mode can only be canceled by a power-on reset. when the ca pin is driven high while the reset breq reset reset 9.7.3 hardware standby mode timing figures 9.10 and 9.11 show examples of pin timing in hardware standby mode. the ca pin is sampled using extal2 (32.768 khz), and a hardware standby request is only recognized when the pin is low for two consecutive clock cycles. the ca pin must be held low while the chip is in hardware standby mode. clock oscillation starts when the ca pin is driven high after the reset ckio ca reset status normal standby reset 0 to 10 bcyc undefined rcyc: extal2 (32.768 khz) cycle 2 rcyc or more figure 9.10 hardware standby mode timing (when ca goes low in normal operation)
167 normal standby undefined reset 0 to 10 bcyc wdt operation standby ckio ca reset status 2 rcyc or more figure 9.11 hardware standby mode timing (when ca goes low during wdt operation on standby mode cancellation)
169 section 10 on-chip oscillation circuits 10.1 overview the clock pulse generator (cpg) supplies all clocks to the processor and controls the power-down modes. the watchdog timer (wdt) is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as frequency changes. it can also be used as an ordinary watchdog timer or interval timer. 10.1.1 features the cpg has the following features: ? six clock modes: selection of six clock modes for different frequency ranges, power consumption, direct crystal input, and external clock input. ? three clocks generated independently: an internal clock for the cpu, cache, and tlb (i?; a peripheral clock (p? for the on-chip supporting modules; and a bus clock (cki0) for the external bus interface. ? frequency change function: internal and peripheral clock frequencies can be changed independently using the pll circuit and divider circuit within the cpg. frequencies are changed by software using frequency control register (frqcr) settings. ? pll on/off function: power consumption can be decreased by stopping the pll circuit when operating at low frequencies. ? power-down mode control: the clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function. the wdt has the following features: ? can be used to ensure the clock settling time: use the wdt to cancel standby mode and the temporary standbys which occur when the clock frequency is changed. ? can switch between watchdog timer mode and interval timer mode. ? generates internal resets in watchdog timer mode: internal resets occur after counter overflow. selection of power-on reset or manual reset. ? generates interrupts in interval timer mode: internal timer interrupts occur after counter overflow. ? selection of eight counter input clocks. eight clocks ( 1 to 1/4096) can be obtained by dividing the peripheral clock.
170 10.2 overview of the cpg 10.2.1 cpg block diagram a block diagram of the on-chip clock pulse generator is shown in figure 10.1. cap1 ckio cycle = bcyc cap2 xtal extal md2 md1 md0 frqcr internal bus bus interface stbcr pll circuit 1 ( 1, 2, 3,4) divider 1 internal clock (i? cycle = icyc peripheral clock (p? cycle = pcyc standby control divider 2 clock pulse generator pll circuit 2 ( 1, 4) crystal oscillator cpg control unit clock frequency control circuit standby control circuit 1 1/2 1/3 1/4 1 1/2 1/3 1/4 frqcr: stbcr: frequency control register standby control register figure 10.1 block diagram of clock pulse generator
171 the clock pulse generator blocks function as follows: 1. pll circuit 1: pll circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock frequency from the ckio terminal. the multiplication rate is set by the frequency control register. when this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the ckio pin. 2. pll circuit 2: pll circuit 2 leaves unchanged or quadruples the frequency of the crystal oscillator or the input clock frequency coming from the extal pin. the multiplication ratio is fixed by the clock operation mode. the clock operation mode is set by pins md0, md1, and md2. see table 10.3 for more information on clock operation modes. 3. crystal oscillator: this oscillator is used when a crystal oscillator element is connected to the xtal and extal pins. it operates according to the clock operating mode setting. 4. divider 1: divider 1 generates a clock at the operating frequency used by the internal clock. the operating frequency can be 1, 1/2, 1/3, or 1/4 times the output frequency of pll circuit 1, as long as it stays at or above the clock frequency of the ckio pin. the division ratio is set in the frequency control register. 5. divider 2: divider 2 generates a clock at the operating frequency used by the peripheral clock. the operating frequencies can be 1, 1/2, 1/3, or 1/4 times the output frequency of pll circuit 1 or the clock frequency of the ckio pin, as long as it stays at or below the clock frequency of the ckio pin. the division ratio is set in the frequency control register. 6. clock frequency control circuit: the clock frequency control circuit controls the clock frequency using the md pin and the frequency control register. 7. standby control circuit: the standby control circuit controls the status of the clock pulse generator and other modules during clock switching and sleep/standby modes. 8. frequency control register: the frequency control register has control bits assigned for the following functions: clock output/non-output from the ckio pin, on/off control of pll circuit 1, pll standby, the frequency multiplication ratio of pll 1, and the frequency division ratio of the internal clock and the peripheral clock. 9. standby control register: the standby control register has bits for controlling the power-down modes. see section 10, power-down modes, for more information.
172 10.2.2 cpg pin configuration table 10.1 lists the cpg pins and their functions. table 10.1 clock pulse generator pins and functions pin name symbol i/o description mode control md0 i set the clock operating mode. pins md1 i md2 i crystal i/o pins xtal o connects a crystal oscillator. (clock input pins) extal i connects a crystal oscillator. also used to input an external clock. clock i/o pin ckio i/o inputs or outputs an external clock. level can be fixed during output. capacitor connection pins cap1 i connects capacitor for pll circuit 1 operation (recommended value 470 pf). for pll cap2 i connects capacitor for pll circuit 2 operation (recommended value 470 pf). 10.2.3 cpg register configuration table 10.2 shows the cpg register configuration. table 10.2 register configuration register name abbreviation r/w initial value address access size frequency control register frqcr r/w h'0102 h'ffffff80 16
173 10.3 clock operating modes table 10.3 shows the relationship between the mode control pin (md2?d0) combinations and the clock operating modes. table 10.4 shows the usable frequency ranges in the clock operating modes. table 10.3 clock operating modes pin values clock i/o pll2 div- pll1 divider 1 divider 2 ckio modemd2 md1 md0 source output on/off ider 3 on/off input input frequency 0 0 0 0 extal ckio on multi- plication ratio: 1 off on pll1 output pll1 (extal) 1 0 0 1 extal ckio on multi- plication ratio: 4 off on pll1 output pll1 (extal) 4 2 0 1 0 crystal oscillator ckio on multi- plication ratio: 4 off on pll1 output pll1 (crystal) 4 3 0 1 1 extal ckio on multi- plication ratio: 1 off off (initial value) pll2 output pll2 (extal) 1 on pll1 output 4 1 0 0 crystal oscillator ckio on multi- plication ratio: 1 off off (initial value) pll2 output pll2 (crystal) 1 on pll1 output 7 1 1 1 ckio off off on pll1 output pll1 (ckio)
174 mode 0: an external clock is input from the extal pin and undergoes waveform shaping by pll circuit 2 before being supplied inside the sh7718r. pll circuit 1 is constantly on, and there are no frequency range restrictions compared to mode 3. an input clock frequency of 16 mhz to 60 mhz can be used, and the ckio frequency range is 16 mhz to 60 mhz. as pll circuit 1 compensates for fluctuations in the ckio pin load, this mode is suitable for connection of synchronous dram. mode 1: an external clock is input from the extal pin and its frequency is multiplied by 4 by pll circuit 2 before being supplied inside the sh7718r, allowing a low-frequency external clock to be used. an input clock frequency of 5 mhz to 15 mhz can be used, and the ckio frequency range is 20 mhz to 60 mhz. as pll circuit 1 compensates for fluctuations in the ckio pin load, this mode is suitable for connection of synchronous dram. mode 2: the on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 4 by pll circuit 2 before being supplied inside the sh7718r, allowing a low crystal frequency to be used. a crystal oscillation frequency of 5 mhz to 15 mhz can be used, and the ckio frequency range is 20 mhz to 60 mhz. as pll circuit 1 compensates for fluctuations in the ckio pin load, this mode is suitable for connection of synchronous dram. mode 3: an external clock is input from the extal pin and undergoes waveform shaping by pll circuit 2 before being supplied inside the sh7718r. pll circuit 1 is off in the default state at power-on reset, and pll circuit 1 can be selected as on or off, enabling power consumption to be kept lower than in mode 0. an input clock frequency of 16 mhz to 25 mhz can be used, and the ckio frequency range is 16 mhz to 25 mhz. mode 4: the on-chip crystal oscillator operates, with its output supplied inside the sh7718r as a square waveform by pll circuit 2. pll circuit 1 is off in the default state at power-on reset, and pll circuit 1 can be selected as on or off, enabling power consumption to be reduced accordingly. a crystal oscillation frequency of 16 mhz to 25 mhz can be used, and the ckio frequency range is 16 mhz to 25 mhz. mode 7: in this mode, the ckio pin is an input, an external clock is input to this pin, and undergoes waveform shaping, and also frequency multiplication according to the setting, by pll circuit 1 before being supplied to the sh7718r. in modes 0 to 6, the system clock is generated from the output of the sh7718r?ckio pin. consequently, if a large number of ics are operating on the clock cycle, the ckio pin load will be large. this mode, however, assumes a comparatively large-scale system. if a large number of ics are operating on the clock cycle, a clock generator with a number of low-skew clock outputs can be provided, so that the ics can operate synchronously by distributing the clocks to each one.
175 as pll circuit 1 compensates for fluctuations in the ckio pin load, this mode is suitable for connection of synchronous dram.
176 table 10.4 range of usable frequencies for each clock operating mode clock mode frqcr pll1 pll2 clock rate* 1 (i:b:p) input frequency range ckio frequency range 0 h'0100 h'0101 h'0102 on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) 1:1:1 1:1:1/2 1:1:1/4 16 mhz to 30 mhz 16 mhz to 60 mhz 16 mhz to 60 mhz 16 mhz to 30 mhz 16 mhz to 60 mhz 16 mhz to 60 mhz h'0111 h'0112 h'0115 h'0116 on ( 2) on ( 2) on ( 2) on ( 2) on ( 1) on ( 1) on ( 1) on ( 1) 2:1:1 2:1:1/2 1:1:1 1:1:1/2 16 mhz to 30 mhz 16 mhz to 50 mhz 16 mhz to 30 mhz 16 mhz to 50 mhz 16 mhz to 30 mhz 16 mhz to 50 mhz 16 mhz to 30 mhz 16 mhz to 50 mhz h'0122 h'0126 h'012a on ( 4) on ( 4) on ( 4) on ( 1) on ( 1) on ( 1) 4:1:1 2:1:1 1:1:1 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz h'a100 h'e100 h'e101 on ( 3) on ( 3) on ( 3) on ( 1) on ( 1) on ( 1) 3:1:1 1:1:1 1:1:1/2 25 mhz to 30 mhz 25 mhz to 30 mhz 25 mhz to 33.3 mhz 25 mhz to 30 mhz 25 mhz to 30 mhz 25 mhz to 33.3 mhz 1, 2 h'0100 h'0101 h'0102 on ( 1) on ( 1) on ( 1) on ( 4) on ( 4) on ( 4) 4:4:4 4:4:2 4:4:1 5 mhz to 7.5 mhz 5 mhz to 15 mhz 5 mhz to 15 mhz 20 mhz to 30 mhz 20 mhz to 60 mhz 20 mhz to 30 mhz h'0111 h'0112 h'0115 h'0116 on ( 2) on ( 2) on ( 2) on ( 2) on ( 4) on ( 4) on ( 4) on ( 4) 8:4:4 8:4:2 4:4:4 4:4:2 5 mhz to 7.5 mhz 5 mhz to 12.5 mhz 5 mhz to 7.5 mhz 5 mhz to 12.5 mhz 20 mhz to 30 mhz 20 mhz to 50 mhz 20 mhz to 50 mhz 20 mhz to 50 mhz h'a100 h'e100 h'e101 on ( 3) on ( 3) on ( 3) on ( 4) on ( 4) on ( 4) 12:4:4 4:4:4 4:4:2 5 mhz to 7.5 mhz 5 mhz to 7.5 mhz 5 mhz to 8.3 mhz 20 mhz to 30 mhz 20 mhz to 30 mhz 20 mhz to 33.3 mhz 3 h'0100 h'0101 h'0102 off off off on ( 1) on ( 1) on ( 1) 1:1:1 1:1:1/2 1:1:1/4 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz h'01d0 h'01d1 h'01d2 h'01d4 h'01d5 h'01d6 on ( 2) on ( 2) on ( 2) on ( 2) on ( 2) on ( 2) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) 2:1:1 2:1:1/2 2:1:1/4 1:1:1 1:1:1/2 1:1:1/4 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz
177 table 10.4 range of usable frequencies for each clock operating mode (cont) clock mode frqcr pll1 pll2 clock rate* 1 (i:b:p) input frequency range ckio frequency range 3 h'81c0 h'81c1 h'c1c0 h'c1c1 on ( 3) on ( 3) on ( 3) on ( 3) on ( 1) on ( 1) on ( 1) on ( 1) 3:1:1 3:1:1/2 1:1:1 1:1:1/2 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz h'01e0 h'01e1 h'01e4 h'01e5 h'01e6 h'01e8 h'01e9 h'01ea on ( 4) on ( 4) on ( 4) on ( 4) on ( 4) on ( 4) on ( 4) on ( 4) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) 4:1:1 4:1:1/2 2:1:1 2:1:1/2 2:1:1/4 1:1:1 1:1:1/2 1:1:1/4 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 4 h'0100 h'0101 h'0102 off off off on ( 1) on ( 1) on ( 1) 1:1:1 1:1:1/2 1:1:1/4 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz h'01d0 h'01d1 h'01d2 h'01d4 h'01d5 h'01d6 on ( 2) on ( 2) on ( 2) on ( 2) on ( 2) on ( 2) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) 2:1:1 2:1:1/2 2:1:1/4 1:1:1 1:1:1/2 1:1:1/4 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz h'81c0 h'81c1 h'c1c0 h'c1c1 on ( 3) on ( 3) on ( 3) on ( 3) on ( 1) on ( 1) on ( 1) on ( 1) 3:1:1 3:1:1/2 1:1:1 1:1:1/2 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz h'01e0 h'01e1 h'01e4 h'01e5 h'01e6 h'01e8 h'01e9 h'01ea on ( 4) on ( 4) on ( 4) on ( 4) on ( 4) on ( 4) on ( 4) on ( 4) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) on ( 1) 4:1:1 4:1:1/2 2:1:1 2:1:1/2 2:1:1/4 1:1:1 1:1:1/2 1:1:1/4 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz 16 mhz to 20 mhz
178 table 10.4 range of usable frequencies for each clock operating mode (cont) clock mode frqcr pll1 pll2 clock rate* 1 (i:b:p) input frequency range ckio frequency range 7 h'0100 h'0101 h'0102 on ( 1) on ( 1) on ( 1) off off off 1:1:1 1:1:1/2 1:1:1/4 16 mhz to 30 mhz 16 mhz to 60 mhz 16 mhz to 60 mhz 16 mhz to 30 mhz 16 mhz to 60 mhz 16 mhz to 60 mhz h'0111 h'0112 h'0115 h'0116 on ( 2) on ( 2) on ( 2) on ( 2) off off off off 2:1:1 2:1:1/2 1:1:1 1:1:1/2 16 mhz to 30 mhz 16 mhz to 50 mhz 16 mhz to 30 mhz 16 mhz to 50 mhz 16 mhz to 30 mhz 16 mhz to 50 mhz 16 mhz to 30 mhz 16 mhz to 50 mhz h'0122 h'0126 h'012a on ( 4) on ( 4) on ( 4) off off off 4:1:1 2:1:1 1:1:1 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz 16 mhz to 25 mhz h'a100 h'e100 h'e101 on ( 3)) on ( 3) on ( 3) off off off 3:1:1 1:1:1 1:1:1/2 25 mhz to 30 mhz 25 mhz to 30 mhz 25 mhz to 33.3 mhz 25 mhz to 30 mhz 25 mhz to 30 mhz 25 mhz to 33.3 mhz notes: 1. input clock frequency is 1 2. max frequency : i ?= 100mhz,b ?= (ckio) = 60mhz,p ?= 30mhz cautions: 1. when clock operating modes 3 and 4 are used: ? the on/off state of pll circuit 1 is set by the frequency control register. ? pll circuit 1 is initialized to the off state by a power-on reset. ? always turn pll circuit 1 off before going into standby mode. 2. the input to divider 1 becomes the output of: ? pll circuit 1 when pll circuit 1 is on. ? pll circuit 2 when pll circuit 1 is off and pll circuit 2 is on. ? divider 3 when pll circuit 1 is off and pll circuit 2 is off. 3. the input of divider 2 becomes the output of: ? pll circuit 1 when the clock operating mode is 0? or 7. ? pll circuit 2 when the clock operating mode is 3 and 4 and pll circuit 2 is on. ? divider 3 when the clock operating mode is 3 and 4 and pll circuit 2 is off. 4. the frequency of the internal clock (i? becomes: ? the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 1 when pll circuit 1 is on. ? equal to the frequency of ckio pin when pll circuit 1 is off.
179 ? do not set the internal clock frequency lower than the ckio pin frequency. 5. the frequency of the peripheral clock (p? becomes: ? the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 2 when the clock operating mode is 0? or 7. ? the product of the frequency of the ckio pin and the division ratio of divider 2 when the clock operating mode is 3 and 4. ? the peripheral clock frequency should not be set higher than the frequency of the ckio pin, higher than 33.3 mhz, or lower than 1/8 the internal clock (i?. 6. the output frequency of pll circuit 1 is the product of the ckio frequency and the multiplication ratio of pll circuit 1. this frequency should be equal to or lower than 100 mhz. 7. 1, 2, 3 or 4 can be used as the multiplication ratio of pll circuit 1. 1, 1/2, and 1/4 can be selected as the division ratios of dividers 1 and 2. set the rate in the frequency control register. the on/off state of pll circuit 2 is determined by the mode. 8. for more in formation about the range of usable freguencies for each clock operating mode,see table 10.4. 10.4 register descriptions 10.4.1 frequency control register (frqcr) the frequency control register (frqcr) is a 16-bit read/write register used to specify whether a clock is output from the ckio pin, the on/off state of pll circuit 1, pll standby, the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. only word access can be used on the frqcr register. frqcr is initialized to h'0102 by a power-on reset, but retains its value in a manual reset and in standby mode. frqcr: bit: 15 14 13 12 11 10 9 8 bit name: stc2 ifc2 pfc2 ckoen initial value: 0 0 0 0 0 0 0 1 r/w: r/w r/w r/w r r r r r/w bit: 7 6 5 4 3 2 1 0 bit name: pllen pstby stc1 stc0 ifc1 ifc0 pfc1 pfc0 initial value: 0 0 0 0 0 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
180 bits 15, 5 and 4?requency multiplication ratio (stc): these bits specify the frequency multiplication ratio of pll circuit 1. bit 15: stc2 bit 5: stc1 bit 4: stc0 description 000 1 (initial value) 001 2 100 3 110 4 note: do not set the output frequency of pll circuit 1 higher than 100mhz. bits 14, 3 and 2?nternal clock frequency division ratio (ifc): these bits specify the frequency division ratio of the internal clock with respect to the output frequency of pll circuit 1. when pll circuit 1 is off or in standby mode, set 1. bit 14: ifc2 bit 2: ifc1 bit 1: ifc0 description 000 1 (initial value) 001 1/2 100 1/3 110 1/4 note: do not set the interunal clock frequency lower then the ckio frequency. bits 13, 1 and 0?eripheral clock frequency division ratio (pfc): these bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of pll circuit 1 or the frequency of the ckio pin. bit 13: pfc2 bit 1: pfc1 bit 0: pfc0 description 000 1 001 1/2 100 1/3 110 1/4 note: do not set the peripheral clock frequency higher then the frequency of the ckio pin. bits 12 to 9?eserved: these bits are always read as 0. the write value should always be 0.
181 bit 8?lock enable (ckoen): used to output a clock from the ckio pin or to fix the level of the ckio pin in clock operation modes 3 and 4. even when the level is fixed, the sh7718r will operate internally at the frequency before the level was fixed. in case of clock operating mode 7, the ckio pin becomes an input pin irrespective of the value of this bit. bit 8: ckoen description 0 fixes the level of ckio terminal. 1 outputs a clock from the ckio pin. (initial value) bit 7?ll circuit enable (pllen): specifies the on/off state of pll circuit 1. this bit is valid in clock operating modes 3 and 4. pll circuit 1 goes on when the clock operating mode is 0? or 7 irrespective of the value of pllen. bit 7: pllen description 0 pll circuit 1 is not used. (initial value) 1 pll circuit 1 is used. bit 6?ll standby (pstby): specifies pll standby. when pll standby is active, pll circuit 1 will be in standby mode at the frequency specified by the stc bit. this function is valid in clock operating modes 3 and 4. bit 6: pstby description 0 pll is not in standby mode. (initial value) 1 pll is in standby mode.
182 10.5 changing the frequency the frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of pll circuit 1 or by changing the division rates of dividers 1 and 2. all of these are controlled by software through the frequency control register. the methods are described below. in modes 3?, the frequency can also be changed by turning pll circuit 1 on and off, as described in section 10.6, pll standby function. 10.5.1 changing the multiplication rate a pll settling time is required when the multiplication rate of pll circuit 1 is changed. the on- chip wdt counts the settling time. 1. in the initial state, the multiplication rate of pll circuit 1 is 1. 2. set a value that will become the specified oscillation settling time in the wdt and stop the wdt. the following must be set: wtcsr register tme bit = 0: wdt stops wtcsr register cks2?ks0 bits: division ratio of wdt count clock wtcnt counter: initial counter value 3. set the desired value in the stc2 and stc0 bits. the division ratio can also be set in the ifc2?fc0 bits and pfc2?fc0 bits. 4. the processor pauses internally and the wdt starts incrementing. in clock modes 0? and 7, the internal and peripheral clocks both stop. in clock modes 3 and 4, only the internal clock stops. the clock will continue to be output at the ckio pin as long as the ckoen bit in the frqcr register is set to 1. 5. supply of the clock that has been set begins at wdt count overflow, and the processor begins operating again. the wdt stops after it overflows. 10.5.2 changing the division ratio the wdt will not count unless the multiplication rate is changed simultaneously. 1. in the initial state, ifc2?fc0 = 000 and pfc2?fc0 = 010. 2. set the ifc2?fc0 and pfc2?fc0 bits to the new division ratio. the values that can be set are limited by the clock mode and the multiplication rate of pll circuit 1. note that if the wrong value is set, the processor will malfunction. 3. the clock is immediately supplied at the new division ratio.
183 10.6 pll standby function 10.6.1 overview of the pll standby function when operating in clock modes 3 and 4, the internal clock can be controlled by turning the pll1 circuit on and off. a long oscillation settling time is required, however, when the pll circuit is started up from a complete halt. during this time, processor operation halts. to enable fast on/off switching of the pll1 circuit, the pll standby function is provided. this function is controlled by software using the frequency control register. the use of the pll standby function is described below. 10.6.2 usage from off to on : 1. initially, pstby = 0, pllen = 0, and pll circuit 1 is stopped. the output of pll circuit 2 is used for divider 1 input. 2. when the multiplication rate of pll circuit 1 is set in the stc2?tc0 bits and pstby is set to 1, pll circuit 1 begins oscillating at the specified multiplication rate. the input to divider 1 is still the output of pll circuit 2 at this point. 3. after pll circuit 1 oscillation has stabilized, the input of divider 1 switches when pllen is set to 1 and the oscillation output of pll circuit 1 is divided and becomes the internal clock. at this time, the division ratio can be changed by changing the settings of ifc2?fc0 and pfc2?fc0. for several cycles before and after the clock switches, the internal clock will be stopped, but the peripheral clock and ckio output do not stop. from on to off : 1. when pllen is set to 0, the input of divider 1 switches to the output of pll circuit 2. at this time, the division ratio can be changed by changing the settings of ifc2?fc0 and pfc2 pfc0. 2. when pstby is set to 0, pll circuit 1 stops. this setting can be performed simultaneously (and with the same instruction as) the setting in 1 above. notes: 1. there are some restrictions on the pll standby state (pstby = 1, pllen = 0) as follows: the settings of the frequency control register? ckoen, stc2?tc0, ifc2?fc0 and pfc2?fc0 bits generally cannot be changed. in some cases, however, they can be changed if the pstby and pllen bit settings are also changed simultaneously (figure 10.2). the sleep instruction cannot be executed. 2. it is the responsibility of software to ensure the oscillation settling time. if pllen is set to 1 before the oscillation has settled, malfunctions may be caused by an unstable clock.
184 3. in clock modes 3 and 4, the sh7718r cannot go to standby mode while pll circuit 1 is on. always set pstby and pllen to 0 to stop pll circuit 1 before going to standby mode. 4. when pstby and pllen are both changed from 0 to 1 together, the wdt will automatically start counting and the clock will switch when the wdt overflows. see section 10.5, changing the frequency, for setting the wdt. pll1 off pll1 standby pstby = 1 (stc) pstby = 0 (stc) pll1 on pllen = 1 (ifc, pfc) pstby = 1 and pllen = 1 pstby = 0, pllen = 0 (stc, ifc, pfc) pstby = 0 and pllen = 0 pstby = 1 and pllen = 0 pllen = 0 (stc, ifc, pfc) note: bits in parentheses can be changed simultaneously. figure 10.2 state transitions for the pll standby function 10.7 controlling clock output the ckoen bit in the frqcr register can be used to switch between outputting a clock to the ckio pin or having the level fixed. 10.7.1 clock modes 0? the ckio pin level cannot be fixed. always set the ckoen bit in frqcr to 1 (clock output). 10.7.2 clock modes 3 and 4 the ckio output changes as soon as the ckoen bit is changed. when the wdt is started by simultaneously changing the multiplication rate of pll circuit 1 or switching pll circuit 1 on or off, the wdt starts running after the ckio output is switched, and then the internal clock changes.
185 10.8 overview of the watchdog timer (wdt) 10.8.1 block diagram of the wdt figure 10.3 shows a block diagram of the wdt. wtcsr standby control bus interface wtcnt divider clock selector clock internal bus standby mode peripheral clock standby cancellation reset control clock selection wdt overflow internal reset request interrupt control interrupt request wtcsr: wtcnt: watchdog timer control/status register watchdog timer counter figure 10.3 block diagram of the wdt 10.8.2 register configurations the wdt has two registers that select the clock, switch the timer mode, and perform other functions. table 10.5 shows the wdt register. table 10.5 register configuration name abbreviation r/w size initial value address watchdog timer counter wtcnt r/w* r: byte; w: word* h'00 h'ffffff84 watchdog timer control/status register wtcsr r/w* r: byte; w: word* h'00 h'ffffff86 note: * write with a word access. write h'5a and h'a5, respectively, in the upper bytes. byte or longword writes are not possible. read with a byte access.
186 10.9 wdt registers 10.9.1 watchdog timer counter (wtcnt) the watchdog timer counter (wtcnt) is an 8-bit read/write counter that increments on the selected clock. when an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. its address is h'ffffff84. the wtcnt counter is initialized to h'00 only by a power-on reset through the reset pin. use a word access to write to the wtcnt counter, with h'5a in the upper byte. use a byte access to read wtcnt. bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 10.9.2 watchdog timer control/status register (wtcsr) the watchdog timer control/status register (wtcsr) is an 8-bit read/write register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. its address is h'ffffff86. the wtcsr register is initialized to h'00 only by a power-on reset through the reset pin. when a wdt overflow causes an internal reset, the wtcsr retains its value. when used to count the clock settling time for canceling a standby, it retains its value after counter overflow. use a word access to write to the wtcsr counter, with h'a5 in the upper byte. use a byte access to read wtcsr. bit: 7 6 5 4 3 2 1 0 tme wt/ it bit 7?imer enable (tme): starts and stops timer operation. clear this bit to 0 when using the wdt in standby mode or when changing the clock frequency. bit 7: tme description 0 timer disabled: count-up stops and wtcnt value is retained 1 timer enabled
187 bit 6?imer mode select (wt/ it ): selects whether to use the wdt as a watchdog timer or an interval timer. bit 6: wt/ it description 0 use as interval timer (initial value) 1 use as watchdog timer note: if wt/ it bit 5?eset select (rsts): selects the type of reset when the wtcnt overflows in watchdog timer mode. in interval timer mode, this setting is ignored. bit 5: rsts description 0 power-on reset (initial value) 1 manual reset bit 4?atchdog timer overflow (wovf): indicates that the wtcnt has overflowed in watchdog timer mode. this bit is not set in interval timer mode. bit 4: wovf description 0 no overflow (initial value) 1 wtcnt has overflowed in watchdog timer mode bit 3?nterval timer overflow (iovf): indicates that the wtcnt has overflowed in interval timer mode. this bit is not set in watchdog timer mode. bit 3: iovf description 0 no overflow (initial value) 1 wtcnt has overflowed in interval timer mode bits 2 to 0?lock select 2? (cks2?ks0): these bits select the clock to be used for the wtcnt count from the eight types obtainable by dividing the peripheral clock. the overflow period in the table is the value when the peripheral clock (p? is 15 mhz.
188 bit 2: cks2 bit 1: cks1 bit 0: cks0 clock division ratio overflow period (when p = 15 mhz) 0001 (initial value) 17 cks0 are modified when the wdt is running, the up-count may not be performed correctly. ensure that these bits are modified only when the wdt is not running. 10.9.3 notes on register access the watchdog timer counter (wtcnt) and watchdog timer control/status register (wtcsr) are more difficult to write to than other registers. the procedure for writing to these registers are given below. writing to wtcnt and wtcsr: these registers must be written by a word transfer instruction. they cannot be written by a byte or longword transfer instruction. when writing to wtcnt, set the upper byte to h'5a and transfer the lower byte as the write data, as shown in figure 10.4. when writing to wtcsr, set the upper byte to h'a5 and transfer the lower byte as the write data. this transfer procedure writes the lower byte data to wtcnt or wtcsr. 15 8 7 0 h'5a write data address: h'fffffe84 wtcnt write 15 8 7 0 h'a5 write data address: h'fffffe86 wtcsr write figure 10.4 writing to wtcnt and wtcsr
189 10.10 using the wdt 10.10.1 canceling standbys the wdt can be used to cancel standby mode with an nmi or other interrupts. the procedure is described below. (the wdt does not run when resets are used for canceling, so keep the reset pin low until the clock stabilizes.) 1. before transitioning to standby mode, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2?ks0 bits in wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. move to standby mode by executing a sleep instruction to stop the clock. 4. the wdt starts counting by detecting the edge change of the nmi signal or detecting interrupts. 5. when the wdt count overflows, the cpg starts supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 6. the counter stops at the values h'00?'01. the stop value depends on the clock ratio. 10.10.2 changing the frequency to change the frequency used by the pll, use the wdt. when changing the frequency only by switching the divider, do not use the wdt. 1. before changing the frequency, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2?ks0 bits of wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. when the frequency control register (frqcr) is written, the clock stops and the processor enters standby mode temporarily. the wdt starts counting. 4. when the wdt count overflows, the cpg resumes supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 5. the counter stops at the values h'00?'01. the stop value depends on the clock ratio.
190 10.10.3 using watchdog timer mode 1. set the wt/ it bit in the wtcsr register to 1, set the reset type in the rsts bit, set the type of count clock in the cks2?ks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in watchdog timer mode. 3. while operating in watchdog timer mode, rewrite the counter periodically to h'00 to prevent the counter from overflowing. 4. when the counter overflows, the wdt sets the wovf flag in wtcsr to 1 and generates the type of reset specified by the rsts bit. the counter then resumes counting. 10.10.4 using interval timer mode when operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. this enables interrupts to be generated at set periods. 1. clear the wt/ it bit in the wtcsr register to 0, set the type of count clock in the cks2 cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in interval timer mode. 3. when the counter overflows, the wdt sets the iovf flag in wtcsr to 1 and an interval timer interrupt request is sent to intc. the counter then resumes counting. 10.11 notes on board design when using an external crystal resonator: place the crystal resonator, capacitors cl1 and cl2, and damping resistor r close to the extal and xtal pins. to prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components.
191 n ote: the values for cl1, cl2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. xtal extal sh7718r r cl2 cl1 avoid crossing signal lines figure 10.5 points for attention when using crystal resonator decoupling capacitors: as far as possible, insert a laminated ceramic capacitor of 0.01 to 0.1 ? as a passive capacitor for each v ss /v cc pair. mount the passive capacitors as close as possible to the lsi power supply pins, and use components with a frequency characteristic suitable for the lsi operating frequency, as well as a suitable capacitance value. digital system v ss /v cc pairs: 6-7, 17-18, 19-20, 30-31, 41-42, 49-50, 54-55, 59-60, 68-69, 82-81,83, 100-102, 115-116, 121-122, 127-128, 144-139 on-chip oscillator v ss /v cc pairs: 73-75, 76-78, 138-135 when using a pll oscillator circuit: keep the wiring from the pll v cc and v ss connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. ground the oscillation stabilization capacitors c1 and c2 to v ss (pll1) and v ss (pll2), respectively. place c1 and c2 close to the cap1 and cap2 pins and do not locate a wiring pattern in the vicinity. in clock mode 7, connect the extal pin to v cc or v ss and leave the xtal pin open.
192 cap2 v cc (pll2) v cc (pll1) v cc c1 = 470 pf c2 = 470 pf v ss cap1 v ss (pll2) v ss (pll1) avoid crossing signal lines power supply reference values c2 c1 figure 10.6 points for attention when using pll oscillator circuit power supply pin wiring: to prevent mutual interference between power supply pins v cc (pll1), v cc (pll2) and power supply pins v ss (pll1), v ss (pll2), use independent wiring patterns for these two systems, and also other digital v cc and v ss pins, from the power supply source. external device connection: when connecting a device such as synchronous dram that requires timing adjustment, since the ac characteristics are based on the connection of a 30 pf capacitive load to the ckio output, the total capacitive load of ckio should be 30 pf or less. if the total capacitive load of the ckio output exceeds 30 pf, a device requiring timing adjustment should be connected directly to ckio, while in the case of a device without stringent timing adjustment requirements, the ckio output should be received by a buffer to allow the total capacitive load of the ckio output to be reduced. cpu ckio sdram total ckio capacitive load figure 10.7 system connection example
193 section 11 bus state controller (bsc) 11.1 overview the bus state controller (bsc) divides physical address space and outputs control signals for various types of memory and bus interface specifications. bsc functions enable the sh7718r to link directly with dram, synchronous dram, pseudo-sram, sram, rom, and other memory storage devices without an external circuit. the bsc also allows direct connection to pcmcia interfaces, simplifying system design and allowing high-speed data transfers in a compact system. 11.1.1 features the bsc has the following features: ? physical address space is divided into seven areas ? a maximum 64 mbytes for each of the seven areas, 0? ? area bus width can be selected by register (area 0 is set by external pin) ? wait states can be inserted using the wait pin ? wait state insertion can be controlled through software. register settings can be used to specify the insertion of 1?0 cycles independently for each area (areas 1 and 2 have a common setting) ? the type of memory connected can be specified for each area, and control signals are output for direct memory connection ? wait cycles are automatically inserted to avoid data bus conflict for continuous memory accesses to different areas or writes directly following reads of the same area ? direct interface to dram ? multiplexes row/column addresses according to dram capacity ? supports burst operation (high-speed page mode, hyper page mode) ? supports cas-before-ras refresh and self-refresh ? performs low power 4-cas-system byte control ? controls timing of dram direct-connection control signals according to register settings ? direct interface to synchronous dram ? multiplexes row/column addresses according to synchronous dram capacity ? supports burst operation ? has both auto-refresh and self-refresh functions ? controls timing of synchronous dram direct-connection control signals according to register setting
194 ? direct interface to pseudo-sram ? supports burst operation (static column mode) ? auto-refresh and self-refresh ? burst rom interface ? insertion of wait states controllable through software ? register setting control of burst transfers ? pcmcia direct-connection interface ? insertion of wait states controllable through software ? burst operation (page mode) ? bus sizing function for i/o bus width (little-endian mode only) ? fine refreshing control ? supports refresh operation immediately after self-refresh operation in low-power dram by means of refresh counter overflow interrupt function ? refresh counter can be used as an interval timer ? interrupt request generated at compare-match ? interrupt request generated at refresh counter overflow 11.1.2 block diagram figure 11.1 shows a block diagram of the bus state controller.
195 wcr1 wcr2 bcr1 module bus bcr2 mcr dcr bsc rfcr rtcnt comparator refresh controller peripheral bus internal bus interrupt controller memory controller area controller wait controller wait cs6 cs0 , ce2a , ce2b bs rd rd/ wr we3 we0 ras cas , casxx cke iciord , iciowr iois16 bus interface rtcsr rtcor pcr wcr: wait state control register rfcr: refresh count register bcr: bus control register rtcnt: refresh timer count register mcr: memory control register rtcor: refresh time constant register dcr: dram control register rtcsr: refresh timer control/status register pcr: pcmcia control register figure 11.1 bsc block diagram
196 11.1.3 pin configuration table 11.1 lists the bsc pins. table 11.1 pin configuration pin name signal i/o description address bus a25?0 o address output data bus d31?24, d15?0 i/o data i/o when port function is used, d31?24 cannot be used. leave these pins open. data bus/port d23?16/ port7?ort0 i/o when port function is not used, data i/o; when port function is used, port (i/o is set by register for each bit) bus cycle start bs o shows start of bus cycle. during burst transfers, asserts every data cycle. chip select 6? cs6 cs0 o chip select signal to indicate area being accessed. cs5 and cs6 can also be used as ce1a and ce1b of pcmcia. read/write rd/ wr o data bus direction indicator signal. dram/synchronous dram/pcmcia write indicator signal. row address strobe ras / ce o when dram/synchronous dram is used, ras signal. when pseudo-sram is used, ce signal. column address strobe cas / casll / oe o when synchronous dram is used, cas signal. when dram is used, cas signal for d7?0. when pseudo-sram is used, oe / rfsh signal. column address strobe lh caslh o when dram is used, cas signal for d15?8 column address strobe hl cashl / cas2l o when dram is used, cas signal for d23?16. when the area 2 dram is being used, cas signal for d7?0. column address strobe hh cashh / cas2h o when dram is used, cas signal for d31?24. when the area 2 dram is being used, cas signal for d15?8.
197 table 11.1 pin configuration (cont) pin name signal i/o description data enable 0 dqmll/ we0 o when synchronous dram is used, selects d7?0. for other memory, d7?0 write strobe signal. data enable 1 dqmlu/ we1 o when synchronous dram is used, selects d15?8. when pcmcia is used, strobe signal that indicates the write cycle. for other memory, d15?8 write strobe signal. data enable 2 dqmul/ we2 / iciord o when synchronous dram is used, selects d23 d16. for other memory, d23?16 write strobe signal. for pcmcia, strobe signal indicating i/o read. data enable 3 dqmuu/ we3 / iciowr o when synchronous dram is used, selects d31 d24. for other memory, d31?24 write strobe signal. for pcmcia, strobe signal indicating i/o write. read rd o strobe signal indicating read cycle wait wait i wait state request signal 16-bit i/o iois16 i signal indicating pcmcia 16-bit i/o. valid only in little-endian mode. (fix low in big-endian mode.) clock enable cke o connected to clock enable control signal of synchronous dram bus release request breq i bus release request signal bus release acknowledgment back o bus release acknowledge signal area 0 bus width, pcmcia card select md3/ ce2a * 1 , md4/ ce2b * 2 i signal controlling bus width of physical space area 0. when pcmcia is used, ce2a and ce2b . endian switching/ low address strobe md5/ ras2 * 3 i/o signal setting endian for all spaces on reset. when area 2 dram is connected, area 2 dram ras signal notes: 1. md3/ ce2a input/output switching is performed by bcr1.a5pcm. output is selected when bcr1.a5pcm = 1. 2. md4/ ce2b input/output switching is performed by bcr1.a6pcm. output is selected when bcr1.a6pcm = 1. 3. md5/ ras2 input/output switching is performed by bcr1.dramtp. output is selected when bcr1.dramtp (2?) = 101.
198 11.1.4 register configuration the bsc has 11 registers (table 11.2). the synchronous dram also has a built-in synchronous dram mode register. these registers control direct connection interfaces to memory, wait states, refreshes, and pcmcia devices. table 11.2 register configuration name abbr. r/w initial value address bus width bus control register 1 bcr1 r/w h'0000 h'ffffff60 16 bus control register 2 bcr2 r/w h'3ffc h'ffffff62 16 wait state control register 1 wcr1 r/w h'3fff h'ffffff64 16 wait state control register 2 wcr2 r/w h'ffff h'ffffff66 16 individual memory control register mcr r/w h'0000 h'ffffff68 16 dram control register dcr r/w h'0000 h'ffffff6a 16 pcmcia control register pcr r/w h'0000 h'ffffff6c 16 refresh timer control/status register rtcsr r/w h'0000 h'ffffff6e 16 refresh timer counter rtcnt r/w h'0000 h'ffffff70 16 refresh time constant register rtcor r/w h'0000 h'ffffff72 16 refresh count register rfcr r/w h'0000 h'ffffff74 16 sdram mode register, area 2 sdmr w h'ffffd000 h'ffffdfff 8 sdram mode register, area 3 h'ffffe000 h'ffffefff note: for details see section 11.2.8, synchronous dram mode register.
199 11.1.5 area overview space allocation: the sh7718r architecture provides for a 32-bit virtual address space. the virtual space is divided into five areas by the value of the upper bits of the address. the physical space is divided into eight areas with a 29-bit address space. virtual space can be allocated at will to physical spaces using a memory management unit (mmu). for details, refer to section 3, memory management unit, which describes area allocation for physical spaces. as shown in table 11.4, the sh7718r can be connected directly to seven areas of memory/pc card, and it outputs chip select signals ( cs0 cs6 , ce2a , ce2b ) for each of them. cs0 is asserted during area 0 access; cs6 is asserted during area 6 access. when dram, synchronous dram, or pseudo-sram is connected to area 2 or 3, signals such as ras , cas , rd/ wr , and dqm are also asserted. when pcmcia interface is selected in area 5 or 6, in addition to cs5 / cs6 , ce2a / ce2b are asserted for the corresponding bytes accessed. for virtual address spaces p0 and p3, when the memory management unit (mmu) is on, any physical address can be generated by the mmu for a virtual address. consequently, figure 11.2 can be applied when the mmu is off, and when the mmu is on and the physical addresses corresponding to virtual addresses are identical except for the top 3 bits. when virtual addresses are translated to arbitrary physical addresses, refer to table 11.3, physical address space map. area 0 ( cs0 nn cs1) nn cs2 nn cs3 nn cs4 nn cs5 nn cs6 n nn nn n figure 11.2 correspondence between virtual address space and physical address space
200 table 11.3 physical address space map area physical address connectable memory capacity access size 0 h'00000000 to h'03ffffff normal memory *1 , burst 64 mbytes 8, 16, 32 *2 h'00000000 + h'20000000 6 1 h'04000000 to h'07ffffff normal memory 64 mbytes 8, 16, 32 *3 h'04000000 + h'20000000 6 2 h'08000000 to h'0bffffff normal memory *1 , 64 mbytes 8, 16, 32 *3, *4 h'08000000 + h'20000000 6 3 h'0c000000 to h'0fffffff normal memory, 64 mbytes 8, 16, 32 *3, *5 h'0c000000 + h'20000000 6 4 h'10000000 to h'13ffffff normal memory 64 mbytes 8, 16, 32 *3 h'10000000 + h'20000000 6 5 *5 h'14000000 to h'15ffffff normal memory, pcmcia, 32 mbytes 8, 16, 32 *3, *6 h'16000000 to h'17ffffff burst rom 32 mbytes h'14000000 + h'20000000 6 6 h'18000000 to h'19ffffff normal memory, pcmcia, 32 mbytes 8, 16, 32 *3, *6 h'1a000000 to h'1bffffff burst rom 32 mbytes h'18000000 + h'20000000 6 7 *7 h'1c000000 + h'20000000 7 notes: 1. memory with an sram, rom, or similar interface 2. memory bus width specified by external pin 3. memory bus width specified by register 4. with synchronous dram interface, bus width is 32 bits only. with dram interface, bus width is 16 bits only. 5. with synchronous dram interface, bus width is 32 bits only. with dram and pseudo-sram interface, bus width is either 16 or 32 bits only. when areas 2 and 3 are both dram interface areas, bus width is 16 bits only. 6. with pcmcia interface, bus width is either 8 or 16 bits only. 7. do not access a reserved area, as operation cannot be guaranteed in this case.
201 area 0: h'00000000 area 1: h'04000000 area 2: h'08000000 area 3: h'0c000000 area 4: h'10000000 area 5: h'14000000 the pcmcia interface is for the memory card only only dram with a 16-bit bus can be connected to area 2 the pcmcia interface is shared by the memory and i/o card area 6: h'18000000 normal memory/ burst rom normal memory normal memory/ synchronous dram, dram normal memory/synchronous dram, dram, pseudo-sram normal memory normal memory/ burst rom/pcmcia normal memory/ burst rom/pcmcia figure 11.3 physical space allocation memory size: the memory size in the sh7718r can be set for each area. in area 0, an external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits). the relationship between the external pins (md4 and md3) and the bus width after a power-on reset is as follows. md4 md3 bus width 0 0 reserved (do not set) 1 8 bits 1 0 16 bits 1 32 bits for areas 1?, byte, word, and longword may be chosen for the bus width using bus control register 2 (bcr2) whenever normal memory, rom, burst rom, or the pcmcia interface is used. when the dram or pseudo-sram interfaces are used, word or longword can be chosen as the bus width using the individual memory control register (mcr). set the bus width to longword with mcr for synchronous dram interfaces. when area 2 is used as a dram area, set the bus widths of areas 2 and 3 to word. when areas 5 and 6 are used as pcmcia interfaces, set the bus width to byte or word. when using the port function, set each of the bus widths to byte or word for all areas. for more information, see section 11.2.2, bus control register 2 (bcr2), and section 11.2.5, individual memory control register (mcr).
202 shadow space: areas 0? are decoded by physical address bits a28?26, which correspond to areas 000 to 110. address bits 31?9 are ignored. this means that the range of area 0 addresses, for example, is h'00000000 to h'03ffffff, and its corresponding shadow space is the address space obtained by adding to it h'20000000 n (n = 1?). the address range for area 7, which is on-chip i/o space, is h'1c000000 to h'1fffffff. the address space h'1c000000 + h'20000000 n?'1fffffff + h'20000000 n (n = 0?) corresponding to the area 7 shadow space is reserved, so should not be used. 11.1.6 pcmcia support the sh7718r supports pcmcia standard interface specifications in physical space areas 5 and 6. the interface supported is basically the ic memory card interface and i/o card interface defined by jeida version 4.2 ( pcmcia 2.1 ). in addition, burst access is supported to enable high-speed access. physical space area 5 supports the ic memory card interface only; area 6 supports both the ic memory card interface and the i/o card interface. table 11.4 pcmcia interface characteristics item characteristics access random access + burst access (rom page mode correspondence added) data bus 8/16 bits memory type mask rom, otprom, eprom, eeprom, flash memory, sram memory capacity maximum 32 mbytes i/o section capacity maximum 32 mbytes other supports dynamic i/o bus sizing* and access to pcmcia interface from both the address translation area and non-address translation area note: * dynamic i/o bus sizing is supported only in little-endian mode. commom memory/attribute memory area 5: h'14000000 area 5: h'16000000 commom memory/attribute memory area 6: h'18000000 i/o space area 6: h'1a000000 figure 11.4 pcmcia space allocation
203 table 11.5 pcmcia support interface ic memory card interface i/o card interface sh7718r pin signal i/o function signal i/o function pin 1 gnd ground gnd ground 2 d3 i/o data d3 i/o data d3 3 d4 i/o data d4 i/o data d4 4 d5 i/o data d5 i/o data d5 5 d6 i/o data d6 i/o data d6 6 d7 i/o data d7 i/o data d7 7 ce1 n ce1 n cs5 nn cs6 oe n oe n rd we pgm n we pgm n we1 bsy ireq n nn n n 18 vpp1 program power vpp1 program/ peripheral power 19 a16 i address a16 i address a16 20 a15 i address a15 i address a15 21 a12 i address a12 i address a12 22 a7 i address a7 i address a7 23 a6 i address a6 i address a6 24 a5 i address a5 i address a5 25 a4 i address a4 i address a4 26 a3 i address a3 i address a3 27 a2 i address a2 i address a2 28 a1 i address a1 i address a1 29 a0 i address a0 i address a0 30 d0 i/o data d0 i/o data d0
204 table 11.5 pcmcia support interface (cont) ic memory card interface i/o card interface sh7718r pin signal i/o function signal i/o function pin 31 d1 i/o data d1 i/o data d1 32 d2 i/o data d2 i/o data d2 33 wp* o write protect iois16 nnn iois16 35 gnd ground gnd ground 36 cd1 n cd1 n nn ce2 n ce2 n ce2a nn ce2b n n n iord n iciord iowr n iciowr n n 52 vpp2 program power vpp2 program/ peripheral power 53 a22 i address a22 i address a22 54 a23 i address a23 i address a23 55 a24 i address a24 i address a24 56 a25 i address a25 i address output from port 57 rfu reserved rfu reserved 58 reset i reset reset i reset output from port
205 table 11.5 pcmcia support interface (cont) ic memory card interface i/o card interface sh7718r pin signal i/o function signal i/o function pin 59 wait n wait n wait inpack n 61 reg n n reg n n n n spkr nn nn n stschg n nn cd2 n cd2 n nn note: the sh7718r does not provide wp support.
206 11.2 bsc registers 11.2.1 bus control register 1 (bcr1) the bus control register 1 (bcr1) is a 16-bit read/write register that sets the functions and bus cycle status for each area. it is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. do not access external memory outside area 0 until bcr1 register initialization is complete. bit: 15 14 13 12 11 10 9 8 bit name: hizmem hizcnt endian a0bst1 a0bst0 a5bst1 initial value: 0 0 0 0 0/1* 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: a5bst0 a6bst1 a6bst0 dram tp2 dram tp1 dram tp0 a5pcm a6pcm initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * samples the value of the external pin designating endian upon a power-on reset. bits 15 and 14?eserved: these bits are always read as 0. the write value should always be 0. bit 13 ?igh-z memory control (hizmem): specifies the state of a25 to a0, bs, cs, rd/wr, we/dqm, rd, md3/ce2a, and md4/ce2b in standby mode. bit 13: hizmem description 0 high-impedance (high-z) in standby mode (initial value) 1 drive state in standby mode bit 12?igh-z control (hizcnt): specifies the state of the ras and cas signals in the standby and bus-released states. bit 12: hizcnt description 0 ras and cas signals become high-impedance (high-z) in standby mode and in bus-released state. (initial value) 1 ras and cas signals drive in standby mode and in bus-released state.
207 bit 11?ndian flag (endian): samples the value of the external pin designating endian upon a power-on reset. endian for all physical spaces is decided by this bit, which is read-only. bit 11: endian description 0 (on reset) endian setting external pin (md5) is low. indicates the sh7718r is set as big-endian. 1 (on reset) endian setting external pin (md5) is high. indicates the sh7718r is set as little-endian. bits 10 and 9?rea 0 burst rom control (a0bst1?0bst0): these bits specify whether to use burst rom in physical space area 0. when burst rom is used, they set the number of burst transfers. bit 10: a0bst1 bit 9: a0bst0 description 0 0 access area 0 as normal memory. (initial value) 1 access area 0 as burst rom (4 consecutive accesses). can be used when bus width is 8, 16, or 32. 1 0 access area 0 as burst rom (8 consecutive accesses). can be used only when bus width is 8 or 16. 1 access area 0 as burst rom (16 consecutive accesses). can be used only when bus width is 8. bits 8 and 7?rea 5 burst enable (a5bst1?5bst0): these bits specify whether to use burst rom and pcmcia burst mode in physical space area 5. when burst rom and pcmcia burst mode are used, they set the number of burst transfers. bit 8: a5bst1 bit 7: a5bst0 description 0 0 access area 5 as normal memory. (initial value) 1 burst access of area 5 (4 consecutive accesses). can be used when bus width is 8, 16, or 32. 1 0 burst access of area 5 (8 consecutive accesses). can be used only when bus width is 8 or 16. 1 burst access of area 5 (16 consecutive accesses). can be used only when bus width is 8. bits 6 and 5?rea 6 burst enable (a6bst1?6bst0): these bits specify whether to use burst rom and pcmcia burst mode in physical space area 6. when burst rom and pcmcia burst mode are used, they set the number of burst transfers.
208 bit 6: a6bst1 bit 5: a6bst0 description 0 0 access area 6 as normal memory. (initial value) 1 burst access of area 6 (4 consecutive accesses). can be used when bus width is 8, 16, or 32. 1 0 burst access of area 6 (8 consecutive accesses). can be used only when bus width is 8 or 16. 1 burst access of area 6 (16 consecutive accesses). can be used only when bus width is 8. bits 4 to 2?rea 2, area 3 memory type (dramtp2, dramtp1, dramtp0): these bits designate the types of memory connected to physical space areas 2 and 3. normal memory, such as rom, sram, or flash ram, can be directly connected. pseudo-sram, dram, and synchronous dram can also be directly connected. bit 4: dramtp2 bit 3: dramtp1 bit 2: dramtp0 description 0 0 0 areas 2 and 3 are normal memory (initial value) 1 area 2: normal memory; area 3: psram 1 0 area 2: normal memory; area 3: sdram 1 areas 2 and 3 are sdram 1 0 0 area 2: normal memory; area 3: dram 1 areas 2 and 3 are dram* 1 0 reserved (cannot be set) 1 reserved (cannot be set) note: * when selecting these bits, set the area 2 and 3 bus widths as word. the md5 pin output is the ras2 n bit 1?rea 5 bus type (a5pcm): designates whether to access physical space area 5 as pcmcia space. bit 1: a5pcm description 0 access physical space area 5 as normal memory. (initial value) 1 access physical space area 5 as pcmcia space.* note: * md3 pin output is ce2a bit 0?rea 6 bus type (a6pcm): designates whether to access physical space area 6 as pcmcia space.
209 bit 0: a6pcm description 0 access physical space area 6 as normal memory. (initial value) 1 access physical space area 6 as pcmcia space.* note: * md4 pin output is ce2b 11.2.2 bus control register 2 (bcr2) bus control register 2 (bcr2) is a 16-bit read/write register that selects the bus size of each area, and whether to use the 8-bit port. it is initialized to h'3ffc by a power-on reset, but is not initialized by a manual reset or in standby mode. do not access external memory outside area 0 until bcr2 register initialization is complete. bit: 15 14 13 12 11 10 9 8 bit name: a6sz1 a6sz0 a5sz1 a5sz0 a4sz1 a4sz0 initial value: 0 0 1 1 1 1 1 1 r/w: r r r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: a3sz1 a3sz0 a2sz1 a2sz0 a1sz1 a1sz0 porten initial value: 1 1 1 1 1 1 0 0 r/w: r/w r/w r/w r/w r/w r/w r r/w bits 15, 14, and 1?eserved: these bits are always read as 0. the write value should always be 0. bits 2n + 1, 2n?rea n (1?) bus size specification (ansz1, ansz0): these bits specify the bus sizes of physical space area n (n = 1 to 6). bit 2n + 1: ansz1 bit 2n: ansz0 bit 0: porten description 0 0 0 reserved (not settable) 1 byte (8-bit) size 1 0 word (16-bit) size 1 longword (32-bit) size (initial value) 0 0 1 reserved (not settable) 1 byte (8-bit) size 1 0 word (16-bit) size 1 reserved (not settable)
210 bit 0?ort function enable (porten): designates whether to use the d23?16 pins as an 8-bit port. when using this function set the bus widths to word or byte in all areas. bit 0: porten description 0 d23 d16 are not used as a port. (initial value) 1 d23 d16 are used as a port. 11.2.3 wait state control register 1 (wcr1) wait state control register 1 (wcr1) is a 16-bit read/write register that specifies the number of idle (wait) state cycles inserted for each area. for some memories, the drive of the data bus may not be turned off quickly even when the read signal from the external device is turned off. this can result in conflicts between data buses when consecutive memory accesses are to different memories or when a write immediately follows a memory read. the sh7718r automatically inserts idle states equal to the number set in wcr1 in those cases. wcr1 is initialized to h'3fff by a power-on reset. it is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 bit name: waitsel * a6iw1 a6iw0 a5iw1 a5iw0 a4iw1 a4iw0 initial value: 0 0 1 1 1 1 1 1 r/w: r/w r r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: a3iw1 a3iw0 a2iw1 a2iw0 a1iw1 a1iw0 a0iw1 a0iw0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * a-mask version only bit 15?ait signal sampling timing specification (waitsel) [a-mask version only] bit 15: waitsel description 0 wait signal is sampled at rise of ckio in this case, the wait signal should be input synchronously (initial value) 1 wait signal is sampled at fall of ckio in this case, the wait signal can be input asynchronously bit 14 ?eserved: this bit is always read as 0. the write value should always be 0.
211 bits 2n + 1, 2n?rea n (6?) intercycle idle specification (aniw1, aniw0): these bits specify the number of idles inserted between bus cycles when switching between physical space area n (6 0) to another space or between a read access to a write access in the same physical space. bit 2n + 1: aniw1 bit 2n: aniw0 description 0 0 1 idle cycle inserted 1 1 idle cycle inserted 1 0 2 idle cycles inserted 1 3 idle cycles inserted (initial value) 11.2.4 wait state control register 2 (wcr2) wait state control register 2 (wcr2) is a 16-bit read/write register that specifies the number of wait state cycles inserted for each area. it also specifies the pitch of data access for burst memory accesses. this allows direct connection of even low-speed memories without an external circuit. wcr2 is initialized to h'ffff by a power-on reset. it is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 bit name: a6w2 a6w1 a6w0 a5w2 a5w1 a5w0 a4w2 a4w1 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: a4w0 a3w1 a3w0 a1-2w1 a1-2w0 a0w2 a0w1 a0w0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
212 bits 15 to 13?rea 6 wait control (a6w2, a6w1, a6w0): these bits specify the number of wait states inserted in physical space area 6. they also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 15: a6w2 bit 14: a6w1 bit 13: a6w0 inserted wait states wait pin number of states per data transfer wait pin 0 0 0 0 ignored 2 enabled 1 1 enabled 2 enabled 1 0 2 enabled 3 enabled 1 3 enabled 4 enabled 1 0 0 4 enabled 4 enabled 1 6 enabled 6 enabled 1 0 8 enabled 8 enabled 1 10 (initial value) enabled 10 enabled bits 12 to 10?rea 5 wait control (a5w2, a5w1, a5w0): these bits specify the number of wait states inserted in physical space area 5. they also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 12: a5w2 bit 11: a5w1 bit 10: a5w0 inserted wait states wait pin number of states per data transfer wait pin 0 0 0 0 ignored 2 enabled 1 1 enabled 2 enabled 1 0 2 enabled 3 enabled 1 3 enabled 4 enabled 1 0 0 4 enabled 4 enabled 1 6 enabled 6 enabled 1 0 8 enabled 8 enabled 1 10 (initial value) enabled 10 enabled
213 bits 9 to 7?rea 4 wait control (a4w2, a4w1, a4w0): these bits specify the number of wait states inserted in physical space area 4. description bit 9: a4w2 bit 8: a4w1 bit 7: a4w0 inserted wait states wait pin 0000 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled 1004 enabled 1 6 enabled 1 0 8 enabled 1 10 enabled (initial value) bits 6 and 5?rea 3 wait control (a3w1, a3w0): these bits specify the number of wait states inserted in physical space area 3. external wait input is enabled only when normal memory is used, and is ignored when dram, synchronous dram, or pseudo-sram is used. ? for normal memory description bit 6: a3w0 bit 5: a3w0 inserted wait states wait pin 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled (initial value) ? for dram, sdram, pseudo-sram description bit 6: a3w1 bit 5: a3n0 dram: cas assert period sdram: cas latency psram: oe , we assert period 00 1 1 1 11 1 1 10 2 2 2 1 3 3 3 (initial value)
214 bits 4 and 3?reas 1 and 2 wait control (a1?w1, a1?w0): these bits specify the number of wait states inserted in physical space areas 1 and 2. external wait input is enabled only when normal memory is used, and is ignored when dram or synchronous dram is used. ? for normal memory description bit 4: a1-2w0 bit 3: a1-2w0 inserted wait states wait pin 0 0 0 ignored 1 1 enabled 1 0 2 enabled 1 3 enabled (initial value) ? for dram, synchronous dram, pseudo-sram description bit 4: a1-2w0 bit 3: a1-2w0 dram: cas assert period sdram: cas latency 00 1 1 11 1 10 2 2 1 3 3 (initial value) bits 2 to 0?rea 0 wait control (a0w2, a0w1, a0w0): these bits specify the number of wait states inserted in physical space area 0. they also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 2: a0w2 bit 1: a0w1 bit 0: a0w0 inserted wait states wait pin number of states per data transfer wait pin 0 0 0 0 ignored 2 enabled 1 1 enabled 2 enabled 1 0 2 enabled 3 enabled 1 3 enabled 4 enabled 1 0 0 4 enabled 4 enabled 1 6 enabled 6 enabled 1 0 8 enabled 8 enabled 1 10 (initial value) enabled 10 enabled
215 11.2.5 individual memory control register (mcr) the individual memory control register (mcr) is a 16-bit read/write register that specifies ras and cas timing and burst control for dram (area 3 only), synchronous dram (areas 2 and 3), and pseudo-sram, specifies address multiplexing, and controls refresh. this enables direct connection of dram, synchronous dram and pseudo-sram without external circuits. mcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bits tpc1, tpc0, rcd1, rcd0, trwl1, trwl0, tras1, tras0, be, sz, amx1, amx0, and edomode are written to in the initialization after a power-on reset and are not then modified again. when rfsh and rmode are written to, write the same values to the other bits. when using dram, pseudo-sram, and synchronous dram, do not access areas 2 and 3 until this register is initialized. bit: 15 14 13 12 11 10 9 8 bit name: tpc1 tpc0 rcd1 rcd0 trwl1 trwl0 tras1 tras0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: be sz amx1 amx0 rfsh rmode edo mode initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w bits 15 and 14?as precharge time (tpc1, tpc0): when dram interface is selected as connected memory, the tpc bits set the minimum number of cycles until the next ras assertion after ras negation. when synchronous dram interface is selected, they set the minimum number of cycles until output of the next bank-active command after precharge. when pseudo- sram interface is selected, they set the minimum number of cycles until the next ce assertion after ce negation. description bit 15: tpc1 bit 14: tpc0 normally immediately after self-refresh 0 0 1 cycle (initial value) 2 cycles (initial value) 1 2 cycles 5 cycles 1 0 3 cycles 8 cycles 1 4 cycles 11 cycles
216 bits 13 and 12?as?as delay (rcd1, rcd0): these bits set the ras cas assert delay time for the connected memory when dram interface is selected. when synchronous dram interface is selected, they set the bank active read/write command delay time. when pseudo-sram interface is selected, they set the ce oe and ce we assert delay. bit 13: rcd1 bit 12: rcd0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 4 cycles bits 11 and 10?rite-precharge delay (trwl1, trwl0): these bits set the synchronous dram write-precharge delay time. this designates the time between the end of a write cycle and the next bank-active command. this is valid only when synchronous dram is connected. after the write cycle, the next bank-active command is not issued for the period tpc + trwl. bit 11: trwl1 bit 10: trwl0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 reserved (cannot be set) bits 9 and 8?as-before-ras refresh ras assert time (tras1, tras0): when dram interface is selected as connected memory, the tras bits set the ras assertion period for cas - before- ras refreshes. when pseudo-sram interface is selected, they set the oe / rfsh assertion period for auto-refreshes. when synchronous dram interface is selected, no bank-active command is issued during the period tpc + tras after an auto-refresh command. bit 9: tras1 bit 8: tras0 description 0 0 2 cycles (initial value) 1 3 cycles 1 0 4 cycles 1 5 cycles bit 7?eserved: this bit is always read as 0. the write value should always be 0.
217 bit 6?urst enable (be): specifies whether to conduct a burst access of dram or pseudo- sram. when accessing synchronous dram, burst access is always carried out, regardless of this bit? designation. bit 6: be description 0 burst disabled (initial value) 1 with dram interface, high-speed page mode access with pseudo-sram interface, continuous data transfer in static column mode bit 5?emory data size (sz): specifies the memory data bus size for dram, synchronous dram, and pseudo-sram. always set this bit to 1 when synchronous dram is used. takes precedence over the bcr2 register designation. bit 5: sz description 0 word (16-bit) (initial value) 1 longword (32-bit) bits 4 and 3?ddress multiplex (amx1, amx0): these bits specify address multiplexing for dram and synchronous dram. the actual address shift value differs between dram interface and synchronous dram interface. for dram interface: bit 4: amx1 bit 3: amx0 description 0 0 8-bit column address product (initial value) 1 9-bit column address product 1 0 10-bit column address product 1 11-bit column address product for synchronous dram interface: bit 4: amx1 bit 3: amx0 description 0 0 16-mbit product (1m
218 bit 2?efresh control (rfsh): determines whether or not refreshing of dram, synchronous dram, and pseudo-sram is performed. the timer for generation of the refresh request frequency can also be used as an interval timer. bit 2: rfsh description 0 no refresh (initial value) 1 refresh bit 1?efresh mode (rmode): selects whether to perform an ordinary refresh or a self-refresh when the rfsh bit is 1. when the rfsh bit is 1 and this bit is 0, a cas-before-ras refresh or an auto-refresh is performed on dram, synchronous dram or pseudo-sram at the period set by the refresh-related registers rtcnt, rtcor and rtcsr. when a refresh request occurs during an external bus cycle, the bus cycle will be ended and the refresh cycle performed. when the rfsh bit is 1 and this bit is also 1, the dram, synchronous dram or pseudo-sram will wait for the end of any executing external bus cycle before going into a self-refresh. all refresh requests to memory that is in the self-refresh state are ignored. bit 1: rmode description 0 cas-before-ras refresh (rfsh must be 1) (initial value) 1 self-refresh (rfsh must be 1) bit 0?extended data out (edomode): specifies the timing of data sampling during data reads when using dram in edo mode. operating timing of memory other than dram does not change even if this bit is set. this bit is valid only for dram connected to area 3. do not set this bit to 1 when using synchronous dram or pseudo-sram. bit 0: edomode description 0 set when using normal dram. data is sampled during read cycle on the falling edge of ckio. (initial value) 1 set when using edo mode dram. data is sampled during read cycle on the rising edge of ckio. also, ras signal negation is delayed 1/2 a ckio machine cycle.
219 11.2.6 dram control register (dcr) the dram area control register (dcr) is a 16-bit read/write register that specifies ras and cas timing and burst control for dram connected to area 2. it also specifies address multiplexing and controls refreshing. when dram is connected to area 2, the bus width is fixed at 16 bits. in such cases, set the area 3 bus width to 16 bits as well. other areas should be 8 bits or 16 bits. dcr is initialized to h'0000 by a power-on reset, but is not initialized by a manual resets or in standby mode. do not access external memory outside area 2 until initialization of this register is complete. bit: 15 14 13 12 11 10 9 8 bit name: tpc1 tpc0 rcd1 rcd0 tras1 tras0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: be amx1 amx0 rfsh rmode initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r r/w r/w r/w r/w r bits 15 and 14?as precharge time (tpc1, tpc0): these bits set the ras precharge time for the dram connected to area 2. description bit 15: tpc1 bit 14: tpc0 normally immediately after self-refresh 0 0 1 cycle (initial value) 2 cycles (initial value) 1 2 cycles 5 cycles 1 0 3 cycles 8 cycles 1 4 cycles 11 cycles bits 13 and 12?as?as delay (rcd1, rcd0): these bits set the ras?as delay time for the dram connected to area 2. bit 13: rcd1 bit 12: rcd0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 4 cycles
220 bits 9 and 8?as-before-ras refresh ras assert time (tras1, tras0): these bits set the ras assert period for cas-before-ras refreshing of the dram connected to area 2. bit 9: tras1 bit 8: tras0 description 0 0 2 cycles (initial value) 1 3 cycles 1 0 4 cycles 1 5 cycles bit 6?urst enable (be): specifies whether to conduct a burst access of the dram connected to area 2. bit 6: be description 0 burst disabled (initial value) 1 high-speed page mode access bits 4 and 3?ddress multiplex (amx1, amx0): these bits specify address multiplexing for the dram connected to area 2. bit 4: amx1 bit 3: amx0 description 0 0 8-bit column address product (initial value) 1 9-bit column address product 1 0 10-bit column address product 1 11-bit column address product bit 2?efresh control (rfsh): determines whether or not refreshing of the dram connected to area 2 is performed . bit 2: rfsh description 0 no refresh (initial value) 1 refresh bit 1?efresh mode (rmode): selects the refresh mode for the dram connected to area 2. bit 1: rmode description 0 cas-before-ras refresh (rfsh must be 1) (initial value) 1 self-refresh (rfsh must be 1)
221 bits 11, 10, 7, 5, and 0?eserved: these bits are always read as 0. the write value should always be 0. 11.2.7 pcmcia control register (pcr) the pcmcia control register (pcr) is a 16-bit read/write register that specifies the oe and we signal assert/negate timing for pcmcia interfaces connected to areas 5 and 6. the oe and we signal assert pulse widths are designated by the wcr2 wait control bits. this register is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 bit name: a5ted1 a5ted0 a6ted1 a6ted0 a5teh1 a5teh0 a6teh1 a6teh0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?eserved: these bits are always read as 0. the write value should always be 0. bits 7 and 6?rea 5 address oe / we assert delay (a5ted1, a5ted0): these bits specify the address to oe / we assert delay time for the pcmcia interface connected to area 5. bit 7: a5ted1 bit 6: a5ted0 description 0 0 0.5 cycle delay (initial value) 1 1.5 cycle delay 1 0 2.5 cycle delay 1 3.5 cycle delay
222 bits 5 and 4?rea 6 address oe / we assert delay (a6ted1, a6ted0): these bits specify the address to oe / we assert delay time for the pcmcia interface connected to area 6. bit 5: a6ted1 bit 4: a6ted0 description 0 0 0.5 cycle delay (initial value) 1 1.5 cycle delay 1 0 2.5 cycle delay 1 3.5 cycle delay bits 3 and 2?rea 5 oe / we negate address delay (a5teh1, a5teh0): these bits specify the oe / we negate address delay time for the pcmcia interface connected to area 5. bit 3: a5teh1 bit 2: a5teh0 description 0 0 0.5 cycle delay (initial value) 1 1.5 cycle delay 1 0 2.5 cycle delay 1 3.5 cycle delay bits 1 and 0?rea 6 oe / we negate address delay (a6teh1, a6teh0): these bits specify the oe / we negate address delay time for the pcmcia interface connected to area 6. bit 1: a6teh1 bit 0: a6teh0 description 0 0 0.5 cycle delay (initial value) 1 1.5 cycle delay 1 0 2.5 cycle delay 1 3.5 cycle delay 11.2.8 synchronous dram mode register (sdmr) the synchronous dram mode register (sdmr) is written to via the synchronous dram address bus and is a virtual 8-bit write-only register. it sets synchronous dram mode for areas 2 and 3. sdmr settings must be made before synchronous dram is accessed. writes to the synchronous dram mode register use the address bus rather than the data bus. if the value to be set is x and the sdmr address is y, the value x is written in the synchronous dram mode register by writing in address x + y. since a0 of the synchronous dram is connected to a2 of the chip and a1 of the synchronous dram is connected to a3 of the chip, the value actually written to the synchronous dram is the x value shifted two bits right. for example, when h'0230 is written to the sdmr register of area 2, random data is written to the address
223 h'fffd000 (address y) + h'08c0 (value x), or h'ffffd8c0. as a result, h'0230 is written to the sdmr register. when h'0230 is written to the sdmr register of area 3, random data is written to the address h'fffe000 (address y) + h'08c0 (value x) or h'ffffe8c0. as a result, h'0230 is written to the sdmr register. the range for value x is h'000 to h'0ffc. address bits bit: 31 12 11 10 9 8 bit name: sdmr address initial value: r/w: w* w* w w bit: 7 6 5 4 3 2 1 0 bit name: initial value: r/w: w w w w w w note: depending on the type of synchronous dram. 11.2.9 refresh timer control/status register (rtcsr) the refresh timer control/status register (rtscr) is a 16-bit read/write register that specifies the refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. rtscr is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. note: the method for writing to rtcor is different from that for general registers to prevent inadvertent overwriting. using a word transfer instruction, place b'10100101 in the upper byte and the write data in the lower byte. for details, see section 10.2.13, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 bit name: cmf cmie cks2 cks1 cks0 ovf ovie lmts initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?eserved: these bits are always read as 0. the write value should always be 0.
224 bit 7?ompare match flag (cmf): status flag that indicates that the values of rtcnt and rtcor match. bit 7: cmf description 0 the values of rtcnt and rtcor do not match. clearing condition: when a refresh is performed after 0 has been written in cmf and rfsh = = = bit 6?ompare match interrupt enable (cmie): enables or disables an interrupt request caused when the cmf bit in rtcsr is set to 1. do not set this bit to 1 when using cas-before-ras refreshing or auto-refreshing. bit 6: cmie description 0 disables the interrupt request caused by cmf (initial value) 1 enables the interrupt request caused by cmf bits 5 to 3?lock select bits (cks2?ks0): these bits select the clock input to rtcnt. the source clock is the external bus clock (bclk). the rtcnt count clock is ckio scaled by the specified ratio. bit 5: cks2 bit 4: cks1 bit 3: cks0 description 0 0 0 disables clock input (initial value) 1 bus clock (ckio)/4 1 0 ckio/16 1 ckio/64 1 0 0 ckio/256 1 ckio/1024 1 0 ckio/2048 1 ckio/4096
225 bit 2?efresh count overflow flag (ovf): status flag that indicates when the number of refresh requests indicated in the refresh count register (rfcr) exceeds the limit set in the lmts bit in rtcsr. bit 2: ovf description 0 rfcr has not exceeded the count limit value set in lmts clearing condition: when 0 is written to ovf (initial value) 1 rfcr has exceeded the count limit value set in lmts setting condition: when the rfcr value has exceeded the count limit value set in lmts* note: * contents do not change when 1 is written to ovf. bit 1?efresh count overflow interrupt enable (ovie): selects whether to suppress generation of interrupt requests by ovf when the ovf bit of rtcsr is set to 1. bit 1: ovie description 0 disables interrupt requests caused by ovf (initial value) 1 enables interrupt requests caused by ovf bit 0?efresh count overflow limit select (lmts): indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (rfcr). when the value rfcr exceeds the value specified by lmts, the ovf flag is set. bit 0: lmts description 0 count limit value is 1024 (initial value) 1 count limit value is 512 11.2.10 refresh timer counter (rtcnt) rtcnt is a 16-bit read/write register containing an 8-bit counter that counts up on an input clock. the clock select bits (cks2?ks0) in rtcsr select the input clock. when rtcnt matches rtcor, the ovf bit in rtcsr is set and rtcnt is cleared. rtcnt is initialized to h'00 by a power-on reset; it continues incrementing after a manual reset; it is not initialized in standby mode, but retains its contents. note: the method for writing to rtcor is different from that for general registers to prevent inadvertent overwriting. using a word transfer instruction, place b'10100101 in the upper byte and the write data in the lower byte. for details, see section 11.2.13, cautions on accessing refresh control related registers.
226 bit: 15 14 13 12 11 10 9 8 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 11.2.11 refresh time constant register (rtcor) the refresh time constant register (rtcor) is a 16-bit read/write register. the values of rtcor and rtcnt (lower 8 bits) are constantly compared. when the values match, the compare match flag (cmf) in rtcsr is set and rtcnt is cleared to 0. when the refresh bit (rfsh) in the individual memory control register (mcr) is set to 1 and the refresh mode is set to cas-before- ras refresh, a memory refresh cycle occurs when the cmf bit is set. rtcor is initialized to h'00 by a power-on reset. it is not initialized by a manual reset or in standby mode, but retains its contents. note: the method for writing to rtcor is different from that for general registers to prevent inadvertent overwriting. using a word transfer instruction, place b'10100101 in the upper byte and the write data in the lower byte. for details, see section 11.2.13, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 11.2.12 refresh count register (rfcr) the refresh count register (rfcr) is a 16-bit read/write register containing a 10-bit counter that increments every time rtcor and rtcnt match. when rfcr exceeds the count limit value set
227 by the lmts bit in rtcsr, the ovf bit in rtcsr is set and rfcr is cleared. rfcr is initialized to h'0000 by a power-on reset. it is not initialized by a manual reset or in standby mode, but retains its contents. note: the method for writing to rfcr is different from that for general registers to prevent inadvertent overwriting. using a word transfer instruction, place b'101001 in the top 6 bits of the upper byte, and the write data in the remaining bits. for details, see section 11.2.13, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 11.2.13 cautions on accessing refresh control related registers rfcr, rtcsr, rtcnt, and rtcor require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 11.5). perform reads and writes using the following methods: 1. when writing to rfcr, rtcsr, rtcnt, or rtcor, use only word transfer instructions. byte transfer instructions cannot be used. when writing to rtcnt, rtcsr, or rtcor, place b'10100101 in the upper byte and the write data in the lower byte. when writing to rfcr, place b'101001 in the top 6 bits and the write data in the remaining bits, as shown in figure 11.5. 2. when reading from rfcr, rtcsr, rtcnt, or rtcor, use a 16-bit access. 0 is read from undefined bits. 15 10 8 rtcsr, rtcnt, rtcor 0 rfcr 7 100101 15 10 10 0 9 1 0 0 1 write data write data figure 11.5 writing to rfcr, rtcsr, rtcnt, and rtcor
228 11.3 bsc operation 11.3.1 endian/access size and data alignment the sh7718r supports both big-endian mode, in which the 0 address is the most significant byte in the byte data, and little-endian mode, in which the 0 address is the least significant byte. switching between the two is designated by an external pin (md5 pin) at the time of a power-on reset. after a power-on reset, big-endian mode is set when md5 is low, and little-endian mode is set when md5 is high. three data bus widths are available for normal memory (byte, word, longword) and two data bus widths (word and longword) for dram and pseudo-sram. only longword is available for synchronous dram. for the pcmcia interface, choose from byte and word. this means data alignment is done by matching the device? data width and endian. the access unit must also be matched to the device? bus width. this also means that when longword data is read from a byte- width device, four read operations must be executed. in the sh7718r, data alignment and conversion of data length is performed automatically between the respective interfaces. tables 11.6 through 11.11 show the relationship between endian, device data width, and access unit. table 11.6 32-bit external device/big endian access and data alignment data bus strobe signal operation d31 d24 d23 d16 d15?8 d7?0 we3 , cashh , dqmuu we2 , cashl , dqmul we1 , caslh , dqmlu we0 , casll , dqmll address 0 byte access data 7 0 asserted address 1 byte access data 7 0 asserted address 2 byte access data 7 0 asserted address 3 byte access data 7 0 asserted address 0 word access data 15 8 data 7 0 asserted asserted address 2 word access data 15 8 data 7 0 asserted asserted address 0 longword access data 31 24 data 23 16 data 15 8 data 7 0 asserted asserted asserted asserted
229 table 11.7 16-bit external device/big endian access and data alignment data bus strobe signal operation d31 d24 d23 d16 d15?8 d7?0 we3 , cashh , dqmuu we2 , cashl , dqmul we1 , caslh , dqmlu we0 , casll , dqmll address 0 byte access data 7 0 asserted address 1 byte access data 7 0 asserted address 2 byte access data 7 0 asserted address 3 byte access data 7 0 asserted address 0 word access data 15 8 data 7 0 asserted asserted address 2 word access data 15 8 data 7 0 asserted asserted address 0 longword access 1st time (address 0) data 31 24 data 23 16 asserted asserted 2nd time (address 2) data 15 8 data 7 0 asserted asserted
230 table 11.8 8-bit external device/big endian access and data alignment data bus strobe signal operation d31 d24 d23 d16 d15?8 d7?0 we3 , cashh , dqmuu we2 , cashl , dqmul we1 , caslh , dqmlu we0 , casll , dqmll address 0 byte access data 7 0 asserted address 1 byte access data 7 0 asserted address 2 byte access data 7 0 asserted address 3 byte access data 7 0 asserted address 0 word access 1st time (address 0) data 15 8 asserted 2nd time (address 1) data 7 0 asserted address 2 word access 1st time (address 2) data 15 8 asserted 2nd time (address 3) data 7 0 asserted address 0 longword access 1st time (address 0) data 31 24 asserted 2nd time (address 1) data 23 16 asserted 3rd time (address 2) data 15 8 asserted 4th time (address 3) data 7 0 asserted
231 table 11.9 32-bit external device/little endian access and data alignment data bus strobe signal operation d31 d24 d23 d16 d15?8 d7?0 we3 , cashh , dqmuu we2 , cashl , dqmul we1 , caslh , dqmlu we0 , casll , dqmll address 0 byte access data 7 0 asserted address 1 byte access data 7 0 asserted address 2 byte access data 7 0 asserted address 3 byte access data 7 0 asserted address 0 word access data 15 8 data 7 0 asserted asserted address 2 word access data 15 8 data 7 0 asserted asserted address 0 longword access data 31 24 data 23 16 data 15 8 data 7 0 asserted asserted asserted asserted
232 table 11.10 16-bit external device/little endian access and data alignment data bus strobe signal operation d31 d24 d23 d16 d15?8 d7?0 we3 , cashh , dqmuu we2 , cashl , dqmul we1 , caslh , dqmlu we0 , casll , dqmll address 0 byte access data 7 0 asserted address 1 byte access data 7 0 asserted address 2 byte access data 7 0 asserted address 3 byte access data 7 0 asserted address 0 word access data 15 8 data 7 0 asserted asserted address 2 word access data 15 8 data 7 0 asserted asserted address 0 longword access 1st time (address 0) data 15 8 data 7 0 asserted asserted 2nd time (address 2) data 31 24 data 23 16 asserted asserted
233 table 11.11 8-bit external device/little endian access and data alignment data bus strobe signal operation d31 d24 d23 d16 d15?8 d7?0 we3 , cashh , dqmuu we2 , cashl , dqmul we1 , caslh , dqmlu we0 , casll , dqmll address 0 byte access data 7 0 asserted address 1 byte access data 7 0 asserted address 2 byte access data 7 0 asserted address 3 byte access data 7 0 asserted address 0 word access 1st time (address 0) data 7 0 asserted 2nd time (address 1) data 15 8 asserted address 2 word access 1st time (address 2) data 7 0 asserted 2nd time (address 3) data 15 8 asserted address 0 longword 1st time (address 0) data 7 0 asserted access 2nd time (address 1) data 15 8 asserted 3rd time (address 2) data 23 16 asserted 4th time (address 3) data 31 24 asserted
234 11.3.2 description of areas area 0: area 0 physical address bits a28?26 are 000. address bits a31?29 are ignored and the address range is h'00000000 + h'20000000 n ?h'03ffffff + h'20000000 n (n = 0?, n = 1? is the shadow space). normal memories such as sram, rom, and burst rom can be connected to this space. byte, word, or longword can be selected as the bus width using external pins. when the area 0 space is accessed, the cs0 signal is asserted. the rd signal that can be used as oe and the we0 we3 signals for write control are also asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a0w2?0w0 bits in wcr2. also, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). when the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2?0 according to the number of waits. area 1: area 1 physical address bits a28?26 are 001. address bits a31?29 are ignored and the address range is h'04000000 + h'20000000 n ?h'07ffffff + h'20000000 n (n = 0?, n = 1? is the shadow space). only normal memories like sram and rom can be connected to this space. byte, word, or longword can be selected as the bus width using the a1sz1?1sz0 bits in bcr2. when the area 1 space is accessed, the cs1 signal is asserted. the rd signal that can be used as oe and the we0 we3 signals for write control are also asserted. the number of bus cycles is selected between 0 and 3 wait cycles using the a12w1?12w0 bits in wcr2. also, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). area 2: area 2 physical address bits a28?26 are 010. address bits a31?29 are ignored and the address range is h'08000000 + h'20000000 n ?h'0bffffff + h'20000000 n (n = 0?, n = 1? is the shadow space). normal memories like sram and rom, as well as dram and synchronous dram, can be connected to this space. byte, word, or longword can be selected as the bus width using the a2sz1?2sz0 bits in bcr2 for normal memory. for synchronous dram, set longword using the sz bit in mcr. when dram is connected to area 2, the bus width is fixed at 16 bits. the bus width for area 3 also needs to be 16 bits, while all other areas must be either 8 bits or 16 bits. when the area 2 space is accessed, the cs2 signal is asserted. when normal memories are connected, the rd signal that can be used as oe and the we0 we3 signals for write control are also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the a12w1 to a12w0 bits in wcr2. when normal memory is connected, only, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ).
235 when synchronous dram is connected, the ras signal, cas signal, rd/ wr signal, and byte control signals dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. control of ras , cas , data timing, and address multiplexing is set with mcr. when dram is connected, the ras2 signal, cas2h signal, cas2l signal, and rd/ wr signal are all asserted and addresses multiplexed. control of ras2 , cas , data timing, and address multiplexing is set with dcr. area 3: area 3 physical address bits a28?26 are 011. address bits a31?29 are ignored and the address range is h'0c000000 + h'20000000 n ?h'0fffffff + h'20000000 n (n = 0?, n = 1? is the shadow space). normal memories like sram and rom, as well as dram, pseudo-sram, and synchronous dram, can be connected to this space. byte, word or longword can be selected as the bus width using the a3sz1?3sz0 bits in bcr2 for normal memory. for dram and pseudo-sram, word or longword can be selected using the sz bit in mcr. when synchronous dram is connected, set to longword using the sz bit in mcr. when area 3 space is accessed, cs3 is asserted. when normal memories are connected, the rd signal that can be used as oe and the we0 we3 signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the a3w1?3w0 bits in wcr2. when normal memory is connected, only, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). when synchronous dram is connected, the ras signal, cas signal, rd/ wr signal, and byte control signals dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. when dram is connected, the ras signal, cashh signal, cashl signal, caslh signal, casll signal, and rd/ wr signal are all asserted and addresses multiplexed. when pseudo-sram is connected, the ce signal, oe / rfsh signal, and we0 , we1 , we2 , and we3 signals are asserted. for all of these, control of ras , cas , and data timing and of address multiplexing is set with mcr. area 4: area 4 physical address bits a28?26 are 100. address bits a31?29 are ignored and the address range is h'10000000 + h'20000000 n ?h'13ffffff + h'20000000 n (n = 0?, n = 1? is the shadow space). only normal memories like sram and rom can be connected to this space. byte, word, or longword can be selected as the bus width using the a4sz1?4sz0 bits in bcr2. when the area 4 space is accessed, the cs4 signal is asserted. the rd signal that can be used as oe and the we0 we3 signals for write control are also asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a4w2?4w0 bits in wcr2. also, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ).
236 area 5: area 5 physical address bits a28?26 are 101. address bits a31?29 are ignored and the address range is the 64 mbytes at h'14000000 + h'20000000 n ?h'17ffffff + h'20000000 n (n = 0?, n = 1? is the shadow space). normal memories like sram and rom as well as burst rom and pcmcia interfaces can be connected to this space. pcmcia interfaces only use their ic memory card interface, so the address range becomes the 32 mbytes at h'14000000 + h'20000000 n ?h'15fffffff + h'20000000 n (n = 0?, n = 1? is the shadow space). for normal memory and burst rom, byte, word, or longword can be selected as the bus width using the a5sz1?5sz0 bits in bcr2. for the pcmcia interface, byte, and word can be selected as the bus width using the a5sz1?5sz0 bits in bcr2. when the area 5 space is accessed and normal memory is connected, the cs5 signal is asserted. the rd signal that can be used as oe and the we0 we3 signals for write control are also asserted. when the pcmcia interface is used, the ce1 signal, ce2 signal, oe signal, and we signal are asserted. the number of bus cycles is selected between 0 and 10 wait cycles using the a5w2?5w0 bits in wcr2. also, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). when a burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2?0 according to the number of waits. the setup and hold times of address/ ce1a / ce2a for the read/write strobe signals can be set within a range of 0.5?.5 cycles using the a5ted1?5ted0 and a5teh1?5teh0 bits in the pcr register. area 6: area 6 physical address bits a28?26 are 101. address bits a31?29 are ignored and the address range is the 64 mbytes at h'18000000 + h'20000000 n ?h'1bffffff + h'20000000 n (n = 0?, n = 1? is the shadow space). normal memories like sram and rom as well as burst rom and pcmcia interfaces can be connected to this space. when the pcmcia interface is used, the ic memory card interface address range is the 32 mbytes at h'18000000 + h'20000000 n ?h'19ffffff + h'20000000 n and the i/o card interface address range is the 32 mbytes at h'1a000000 + h'20000000 n h'1bffffff + h'20000000 n (n = 0?, n = 1? is the shadow space). for normal memory and burst rom, byte, word, or longword can be selected as the bus width using the a6sz1?6sz0 bits in bcr2. for the pcmcia interface, byte, and word can be selected as the bus width using the a6sz1?6sz0 bits in bcr2. when the area 6 space is accessed and normal memory is connected, the cs6 signal is asserted. the rd signal that can be used as oe and the we0 we3 signals for write control are also asserted. when the pcmcia interface is used, the ce1b signal, ce2b signal, oe signal, and we1 , icord , and icowr signals are asserted.
237 the number of bus cycles is selected between 0 and 10 wait cycles using the a6w2?6w0 bits in wcr2. also, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). when the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2?0 according to the number of waits. the setup and hold times of address/ ce1b / ce2b for the read/write strobe signals can be set within a range of 0.5?.5 cycles using a6ted1?6ted0 and a6teh1?6teh0. 11.3.3 basic interface basic timing: the basic interface of the sh7718r uses strobe signal output because mainly sram will be directly connected. figure 11.6 shows the basic timing of normal space accesses. a no-wait normal access is completed in two cycles. the bs signal is asserted for one cycle to indicate the start of a bus cycle. the csn signal is negated on the t2 clock falling edge to secure the negation period. therefore, at minimum pitch, there is a half-cycle negation period. there is no access size specification when reading. the correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in a 32-bit device, and 16 bits in a 16-bit device. when writing, only the we signal for the byte to be written is asserted. for details, see section 11.3.1, endian/access size and data alignment. read/write for cache fill or copy-back follows the set bus width and transfers a total of 16 bytes continuously. the bus is not released during this transfer. for cache misses that occur during byte or word operand accesses or branching to odd word boundaries, the fill is always performed by longword accesses on the chip-external interface. write-through area write access and noncacheable read/write access is based on the actual address size.
238 t1 ckio a25 to a0 csn wr rd nnn wen nn bs figure 11.6 basic timing of basic interface
239 figures 11.7, 11.8, and 11.9 show examples of connection to 32-, 16-, and 8-bit data width sram. a16 a0 cs oe we a18 a2 csn rd we3 we2 we1 we0 n a16 a0 cs oe we a16 a0 cs oe we a16 a0 cs oe we figure 11.7 example of 32-bit data width sram connection
240 a16 a0 cs oe we a17 a1 csn rd we1 we0 n a16 a0 cs oe we figure 11.8 example of 16-bit data width sram connection
241 a16 a0 csn rd we0 n a16 a0 cs oe we figure 11.9 example of 8-bit data width sram connection
242 wait state control: wait state insertion on the basic interface can be controlled by the wcr2 settings. if the wcr2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. for details, see section 11.2.4, wait control register 2 (wcr2). the specified number of tw cycles is inserted as wait cycles using the basic interface wait timing shown in figure 11.10. t1 ckio a25 to a0 csn wr rd nn wen nn bs figure 11.10 basic interface wait timing (software wait only)
243 when software wait insertion is specified by wcr2, the external wait input wait signal is also sampled. wait pin sampling is shown in figure 11.11. a 2-cycle wait is specified as a software wait. sampling is performed at the transition from the tw state to the t2 state; therefore, the wait signal has no effect if asserted in the t1 cycle or the first tw cycle. the wait signal is sampled on the rising edge of the clock. t1 ckio a25 to a0 csn wr rd nn wen nn wait bs nnn n wait n figure 11.11 basic interface wait state timing (wait state insertion by wait signal)
244 when the waitsel bit in the wcr1 register is set to 1, the wait signal is sampled at the fall of the clock. if the setup time and hold times with respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge is used. t1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen d31 to d0 wait tw tw tw t2 read write bs wait states inserted by wait signal figure 11.12 basic interface wait state timing (wait state insertion by wait signal, waitsel = 1)
245 11.3.4 dram interface dram connection method: when the memory type bits (dramtp2?ramtp0) in bcr1 are set to 100, area 3 becomes dram space; when set to 101, area 2 and area 3 become dram space. the dram interface function can then be used to connect the sh7718r directly to dram. 16 or 32 bits can be selected as the interface data width for area 3 when bits dramtp2 to dramtp0 are set to 100, and 16 bits can be used for both area 2 and area when bits dramtp2 to dramtp0 are set to 101. 2-cas 16-bit drams can be connected, since cas is used to control byte access. signals used for connection when dram is connected to area 3 are ras , cashh , cashl , caslh , casll , and rd/ wr . cashh and cash l are not used when the data width is 16 bits. when dram is connected to areas 2 and 3, the signals for area 2 dram connection are ras2 , cas2h , cas2l , and rd/ wr , and those for area 3 dram connection are ras , caslh , casll , and rd/ wr . in addition to normal read and write access modes, high-speed page mode is supported for burst access. also, for dram connected to area 3, edo mode, which enables the dram access time to be increased by delaying the data sampling timing by 1/2 clock when reading, is supported in addition to normal read and write access for burst mode.
246 a10 a2 ras wr cashh cashl caslh casll n a8 a0 ras oe we ucas lcas a8 a0 ras oe we ucas lcas figure 11.13 example of dram connection (32-bit data width)
247 a9 a1 ras ras2 wr caslh casll cas2h cas2l n a8 a0 ras oe we ucas lcas a8 a0 ras oe we ucas lcas figure 11.14 example of dram connection (16-bit data width)
248 address multiplexing: when areas 2 and 3 are designated as dram space, address multiplexing is always performed in accesses to dram. this enables dram, which requires row and column address multiplexing, to be connected directly to the sh7718r without using an external address multiplexer circuit. any of the four multiplexing methods shown below can be selected by setting bits amx1 and amx0 in mcr for area 3 dram, or bits amx1 and amx0 in dcr for area 2 dram. the relationship between bits amx1 and amx0 and address multiplexing is shown in table 11.12. the address output pins subject to address multiplexing are a15 to a1. pins a25 to a16 carry the original address. table 11.12 relationship between amx1-0 and address multiplexing setting number of column amx1 amx0 address bits output timing external address pins 0 0 8 bits column address a1 to a14 a15 row address a9 to a22 a23 0 1 9 bits column address a1 to a14 a15 row address a10 to a23 a24 1 0 10 bits column address a1 to a14 a15 row address a11 to a24 a25 1 1 11 bits column address a1 to a14 a15 row address a12 to a25 a15
249 basic timing: figure 11.15 shows the basic timing for dram access is 3 cycles. tpc is the precharge cycle, tr the ras assert cycle, tc1 the cas assert cycle, and tc2 the read data latch cycle. ckio rd/ wr nn nn ras casxx bs cs2 nn cs3 nn nn figure 11.15 basic timing for dram access
250 wait state control: as the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. therefore, provision is made for state extension by using the setting bits in wcr2, mcr, and dcr. the timing with state extension using these settings is shown in figure 11.16. up to four additional tpc cycles (cycles used to secure the ras precharge time) can be inserted by means of the tpc bits in mcr and dcr. the number of cycles from ras assertion to cas assertion can be set to between 1 and 4 by inserting trw cycles by means of the rcd bits in mcr and dcr. the number of cycles from cas assertion to the end of the access can be varied between 1 and 3 according to the setting of a1?w (1,0) or a3w (1,0) in wcr2.
251 ckio rd/ wr nn nn ras casxx bs cs2 nn cs3 nn nn n n n figure 11.16 dram wait state timing
252 burst access: in addition to the normal dram access mode in which a row address is output in each data access, a high-speed page mode is also provided in cases where consecutive accesses are made to the same row. this mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access. normal access or burst access using high-speed page mode can be selected by means of the burst enable (be) bit in mcr and dcr. the timing for burst access using high-speed page mode is shown in figure 11.17. in burst transfer, 4 (longword access) or 16 (cache fill or cache write-back) bytes of data are burst- transferred in a 16-bit bus size. with a 32-bit bus size, 16 bytes of data are burst-transferred (cache fill or cache write-back). in a 16-byte burst transfer (cache fill), the first access comprises a longword that includes the data requiring access. the remaining accesses are performed on 16- byte boundary data that includes the relevant data. in burst transfer (cache write-back), sequential writing is performed if first-to-last order for 16-byte boundary data.
253 ckio rd/ wr nn nn ras casxx bs cs2 nn cs3 nn nn n n n n n figure 11.17 dram burst access timing
254 edo mode: in dram, an extended data out (edo) mode is also provided in which, once the cas signal is asserted while the ras signal is asserted, even if the cas signal is negated, data is output to the data bus until the cas signal is next asserted. (this is in addition to the mode in which data is output to the data bus only while the cas signal is asserted in a data read cycle.) in the sh7718r, the edo mode bit (edomode) in mcr enables selection, for area 3 dram only, of either normal access/burst access using high-speed page mode or edo mode normal access/burst access. edo mode normal access is shown in figure 11.18, and burst access in figure 11.19. in edo mode, the timing for data output to the data bus in a read cycle is extended as far as the next assertion of the cas signal. this delays the data latch timing by 1/2 cycle to the rising edge of the ckio clock, enabling the dram access time to be increased.
255 tr tc1 tc2 (tpc) ckio a25 a16 a15 a0 rd/ wr ras casxx d0 (read) d31 d0 (write) bs cs2 nn cs3 n n n figure 11.18 normal access timing in dram edo mode
256 ckio rd/ wr nn nn ras casxx bs cs2 nn cs3 nn nn n n n n n figure 11.19 burst access timing in dram edo mode
257 refresh timing: the bus state controller includes a function for controlling dram refreshing. refreshing using a cas-before-ras cycle can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr for area 3 dram, or by clearing the rmode bit to 0 and setting the rfsh bit to 1 in dcr for area 2 dram. when cas-before-ras refresh cycles are executed, refreshing is performed at intervals determined by the input clock selected by bits cks2?ks0 in rtcsr, and the value set in rtcor. the value of bits cks2?ks0 in rtcor should be set so as to satisfy the stipulation for the dram refresh interval. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in mcr, then make the cks2?ks0 setting. when the clock is selected by cks2 to cks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated and the irqout pin goes low. if the sh7718r?external bus can be used, cas-before- ras refreshing is performed, and if there is no other interrupt request the irqout pin goes high. at the same time, rtcnt is cleared to zero and the count-up is restarted. figure 11.20 shows the operation of cas-before-ras refreshing. rtcor value rtcnt h'00000000 rtcsr.cks(2 0) cmf external bus cmf flag cleared by start of refresh cycle = 000 figure 11.20 cas-before-ras refresh operation
258 figure 11.21 shows the timing of the cas-before-ras refresh cycle. the number of ras assert cycles in the refresh cycle is specified by the tras bits in mcr and dcr. the specification of the ras precharge time in the refresh cycle is determined by the setting of the tpc bits in mcr and dcr in the same way as for normal access. trc trr1 trr2 (tpc) ckio rd/ wr ras casxx cs2 nn cs3 figure 11.21 dram cas-before-ras refresh cycle timing the self-refreshing supported by the sh7718r is shown in figure 11.22. after the self-refresh is cleared, the refresh controller immediately generates a refresh request. the ras precharge time immediately after the end of the self-refreshing can be set by the tpc bits in mcr and dcr. drams include low-power products (l versions) with a long refresh cycle time (for example, the l version of the hm51w4160al has a refresh cycle of 1024 cycles/128 ms compared with 1024 cycles/16 ms for the normal version). with these drams, however, the same refresh cycle as the normal version is requested only when refreshing immediately after self-refreshing. therefore, to ensure efficient dram refreshing, an overflow interrupt is generated and the refresh cycle is restored to its proper value. this occurs after the necessary cas-before-ras refreshing has been performed following self-refreshing of an l-version dram, using rfcr and the ovf, ovie, and lmts bits in rtcsr. the procedure is as follows.
259 1. normally, set the refresh counter count value to the optimum value for the l version (e.g. 1024 cycles/128 ms). 2. when a transition is made to self-refreshing: a. provide an interrupt handler to restore the refresh counter count value to the optimum value for the l version (e.g. 1024 cycles/128 ms) when a refresh counter overflow interrupt is generated. b. reset the refresh counter count value to the requested short cycle (e.g. 1024 cycles/16 ms), set refresh controller overflow interruption, and clear the refresh count register (rfcr) to 0. c. set self-refresh mode. this procedure causes refreshing immediately following a self-refresh to occur in a short cycle. when adequate refreshing ends, an interrupt is generated and the setting can be restored to the original refresh cycle. cas-before-ras refreshing is performed in normal operation, in sleep mode, and in a manual reset. self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual reset. when the bus has been released in response to a bus arbitration request, or when a transition is made to standby mode, signals generally become high-impedance. controlling the ras and cas signals to become high-impedance or continue to be output is performed with the hizcnt bit in bcr1. this enables the dram to be kept in the self-refreshing state.
260 trc trr1 trrw tsr1 tsr1 tsr2 (tpc) ckio rd/ wr ras casxx cs2 nn cs3 figure 11.22 dram self-refresh cycle timing power-on sequence: for dram after powering on, a minimum wait time of 100 ? or 200 ?, or more during which no access can be performed, should be provided, followed by the prescribed number (usually 8 or more) of dummy cas-before-ras refresh cycles. as the bus state controller does not perform any special operations for a power-on reset, the power-on sequence must be carried out by the initialization program executed after a power-on reset.
261 11.3.5 synchronous dram interface synchronous dram direct connection: since synchronous dram can be selected by the cs signal, physical space areas 2 and 3 can be connected using ras and other control signals in common. if the memory type bits (dramtp2?ramtp0) in bcr1 are set to 010, area 2 is normal memory space and area 3 is synchronous dram space; if set to 011, areas 2 and 3 are both synchronous dram space. with the sh7718r, burst length 1 burst read/single write mode is supported as the synchronous dram operating mode. the data bus width is fixed at 32 bits, and the size bit (sz) in mcr must be set to 1. the burst enable bit (be) in mcr is ignored, a16-bit burst transfer is performed in a cache fill/copy-back cycle, and only one access is performed in a write-through area write or a noncacheable area read/write. the control signals for direct connection of synchronous dram are ras , cas , rd/ wr , cs2 or cs3 , dqmuu, dqmul, dqmlu, dqmll, and cke. all the signals other than cs2 and cs3 are common to all areas, and signals other than cke are valid and fetched to the synchronous dram only when cs2 or cs3 is asserted. synchronous dram can therefore be connected in parallel to a number of areas. cke is negated (low) only when self-refreshing is performed, otherwise it is asserted (high). commands for synchronous dram are specified by ras , cas, rd/ wr , and special address signals. the commands are nop, auto-refresh (ref), self-refresh (self), precharge all banks (pall), precharge specified bank (p re), row address strobe bank active (actv), read (read), read with precharge (reada), write (writ), write with precharge (writa), and mode register write (mrs). byte specification is performed by dqmuu, dqmul, dqmlu, and dqmll. a read/write is performed for the byte for which the corresponding dqm is low. in big-endian mode, dqmuu specifies an access to address 4n, and dqmll specifies an access to address 4n + 3. in little- endian mode, dqmuu specifies an access to address 4n + 3, and dqmll specifies an access to address 4n. figure 11.23 shows an example of the connection of 256k 16-bit synchronous drams.
262 a11 a2 cki0 cke csn ras cas wr n a9 a0 clk cke cs ras cas we a9 a0 clk cke cs ras cas we figure 11.23 example of synchronous dram connection
263 address multiplexing: synchronous dram can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits amx1 and amx0 in mcr. table 11.13 shows the relationship between the address multiplex specification bits and the bits output at the address pins. a25?16 and a0 are not multiplexed; the original values are always output at these pins. when a0, the lsb of the synchronous dram address, is connected to the sh7718r, it performs longword address specification. connection should therefore be made in this order: connect pin a0 of the synchronous dram to pin a2 of the sh7718r, then connect pin a1 to pin a3. table 11.14 shows the example of correspondence between sh7718r and synchronous dram address pins. table 11.13 relationship between sz, amx, and address multiplex output setting external address pins amx1 amx0 output timing a1 to a8 a9 a10 a11 a12 a13 a14 a15 0 0 column address a1 to a8 a9 a10 a11 a12* 1 a13* 2 a14 a15 row address a9 to a16 a17 a18 a19 a20 a21* 2 a22 a23 0 1 column address a1 to a8 a9 a10 a11 l/h* 1 a22* 2 a14 a15 row address a10 to a17 a18 a19 a20 a21 a22* 2 a23 a24 1 0 column address a1 to a8 a9 a120 a11 l/h* 1 a23* 2 a14 a15 row address a11 to a18 a19 a20 a21 a22 a23* 2 a24 a25 1 1 column address a1 to a8 a9 l/h* 1 a19* 2 a12 a13 a14 a15 row address a9 to a16 a17 a18 a19* 2 a20 a21 a22 a23 notes: 1. l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. 2. bank address specification.
264 table 11.14 example of correspondence between sh7718r and synchronous dram address pins (amx (1-0) = 11) sh7718r address pin synchronous ras cycle cas cycle dram address pin function a11 a19 a19 a9 bank select bank address a10 a18 l/h a8 address precharge setting a9 a17 a9 a7 address a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 a1 a9 a1 not used a0 a0 a0 not used burst read: the timing chart for a burst read is shown in figure 11.24. in the following example it is assumed that four 2m 8-bit synchronous drams are connected and a 32-bit data width is used, and the burst length is 1. following the tr cycle in which actv command output is performed, a read command is issued in the tc1, tc2, and tc3 cycles, and a reada command in the tc4 cycle. the read data is then accepted on the rising edge of the external command clock (ckio) from cycle td1 to cycle td4. the tpc cycle is used to wait for completion of auto- precharge based on the reada command inside the synchronous dram; no new access command can be issued to the same bank during this cycle, but access to synchronous dram for another area is possible. in the sh7718r, the number of tpc cycles is determined by the tpc bit specification in mcr, and commands cannot be issued for the same synchronous dram during this interval. the example in figure 11.24 shows the basic timing. to connect slower synchronous dram, the cycle can be extended by setting the wcr2 and mcr bits. the number of cycles from the actv command output cycle, tr, to the read command output cycle, tc1, can be specified by the rcd bit in mcr, with a value of 0 to 3 specifying 1 to 4 cycles, respectively. for 2 or more cycles, a trw cycle, in which an nop command is issued for the synchronous dram, is inserted between the tr cycle and the tc cycle. the number of cycles from read and reada command output cycles tc1?c4 to the first read data latch cycle, td1, can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of a1?w1 and a1?w0 or a3w1 and a3w0 in wcr2. this number of cycles corresponds to the number of synchronous dram cas latency cycles.
265 ckio a25 to a16, a13 a12 a15, a14, a11 to a0 cs2 nn cs3 ras cas wr nn bs figure 11.24 basic timing for synchronous dram burst read
266 figure 11.25 shows the burst read timing when rcd is set to 1, a3w1 and a3w0 are set to 11, and tpc is set to 1. the bs cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is asserted in each of cycles td1?d4 in a synchronous dram cycle. when a burst read is performed, the address is updated each time cas is asserted. as the unit of burst transfer is 16 bytes, address updating is performed for a3 and a2 only. in a fill operation in the event of a cache miss, the order of access is: the missed data is read first, then 16-byte boundary data including the missed data is read in wraparound mode. ckio a25 to a16, a13 a12 a15, a14, a11 to a0 cs2 nn cs3 ras cas wr nn bs figure 11.25 synchronous dram burst read wait specification timing
267 single read: figure 11.26 shows the timing when a single address read is performed. as the burst length is set to 1 in synchronous dram burst read/single write mode, only the required data is output. consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. ckio a25 to a16, a13 a12 a15, a14, a11 to a0 cs2 nn cs3 ras cas wr nn bs figure 11.26 basic timing for synchronous dram single read
268 burst write: the timing chart for a burst write is shown in figure 11.27. in the sh7718r, a burst write occurs only in the event of cache copy-back. in a burst write operation, following the tr cycle in which actv command output is performed, a writ command is issued in the tc1, tc2, and tc3 cycles, and a writa command that performs auto-precharge is issued in the tc4 cycle. in the write cycle, the write data is output at the same time as the write command. for the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is added as a wait interval until precharging is started, following the write command. issuance of a new command for the same bank is postponed during this interval. the number of trwl cycles can be specified by the trwl bit in mcr.
269 ckio csn wr ras casxx nn bs n n n nn n n figure 11.27 basic timing for synchronous dram burst write
270 single write: the basic timing chart for write access is shown in figure 11.28. in a single write operation, following the tr cycle in which actv command output is performed, a writa command that performs auto-precharge is issued in the tc1 cycle. in the write cycle, the write data is output at the same time as the write command. for the write with auto-precharge command, precharging of the relevant bank is performed in synchronous dram after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the write command. issuance of a new command for the same bank is postponed during this interval. the number of trwl cycles can be specified by the trwl bit in mcr.
271 ckio csn wr ras cas nn bs n n nn n n figure 11.28 basic timing for synchronous dram single write
272 refreshing: the bus state controller is provided with a function for controlling synchronous dram refreshing. auto-refreshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr. if synchronous dram is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the rmode bit and the rfsh bit to 1. 1. auto-refreshing refreshing is performed at intervals determined by the input clock selected by bits cks2?ks0 in rtcsr, and the value set in rtcor. the value of bits cks2?ks0 in rtcor should be set so as to satisfy the refresh interval stipulation for the synchronous dram used. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in mcr, then make the cks2 to cks0 setting. when the clock is selected by cks2?ks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. at the same time, rtcnt is cleared to zero and the count-up is restarted. figure 11.29 shows the auto refresh operation. figure 11.30 shows the auto-refresh cycle timing. first, an ref command is issued in the trr cycle. after the trr cycle, new command output cannot be performed for the duration of the number of cycles specified by the tras bits in mcr plus the number of cycles specified by the tpc bits in mcr. the tras and spc bits must be set to satisfy the synchronous dram refresh cycle time stipulation (active/active command delay time). auto-refreshing is performed in normal operation, in sleep mode, and in a manual reset. rtcor value rtcnt h'00000000 rtcsr.cks(2 0) cmf external bus cmf flag cleared by start of refresh cycle = 000 figure 11.29 auto-refresh operation
273 ckio cke csn ras casxx wr figure 11.30 synchronous dram auto-refresh timing 2. self-refreshing self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous dram. self-refreshing is activated by setting both the rmode bit and the rfsh bit to 1. the self-refresh state is maintained while the cke signal is low. synchronous dram cannot be accessed while in the self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the tpc bits in mcr. self-refresh timing is shown in figure 11.31. settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. when self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if rfsh is set to 1 and rmode is cleared to 0 when self-refresh mode is cleared. if the transition from clearing of self- refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of rtcnt. making the rtcnt value 1 less than the rtcor value will enable refreshing to be started immediately. after self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the sh7718r? standby function, and is maintained even after recovery from standby mode other than through a power-on reset. for a power-on reset, the bus state controller? registers are initialized, thereby clearing the self-refresh state.
274 self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual reset. ckio cke csn ras casxx wr figure 11.31 synchronous dram self-refresh timing 3. relationship between refresh requests and bus cycle requests if a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. if a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. if a match between rtcnt and rtcor occurs while a refresh is waiting to be executed, thereby generating a new refresh request, the previous refresh request is eliminated. to perform normal refreshing, ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. when a refresh request is generated, the irqout pin is asserted (driven low). therefore, normal refreshing can be performed by having the irqout pin monitored by a bus master other than the sh7718r requesting the bus, or the bus arbiter, and returning the bus to the sh7718r. when refreshing is started, and if no other interrupt request has been generated, the irqout pin is negated (driven high).
275 power-on sequence: in order to use synchronous dram, mode setting must first be performed after powering on. to perform synchronous dram initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous dram mode register. in synchronous dram mode register setting, the address signal value at that time is latched by a combination of the ras , cas , and rd/ wr signals. if the value to be set is x, the bus state controller provides for value x to be written to the synchronous dram mode register by performing a write to address h'ffffd000 + x for area 2 synchronous dram, and to address h'ffffe000 + x for area 3 synchronous dram. in this operation the data is ignored, but the mode write is performed as a byte-size access. to set burst read/write, cas latency 1 to 3, wrap type = sequential, and burst length 1 supported by the sh7718r, arbitrary data is written in a byte- size access to the following addresses: area 2 area 3 cas latency 1 cas latency 2 cas latency 3 ffffd840 ffffd880 ffffd8c0 ffffe840 ffffe880 ffffe8c0 mode register setting timing is shown in figure 11.32. as a result of the write to address h'ffffd000 + x or h'ffffe000 + x, a precharge all banks (pall) command is first issued in the trp1 cycle, then a mode register write command is issued in the tmw1 cycle. before mode register setting, a 100 ? idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous dram. if the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. the number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. this is usually achieved automatically through various initialization methods after auto-refresh setting. however, a more dependable method is to set a short refresh request generation interval just as these dummy cycles are being executed. with simple read or write access, the address counter in the synchronous dram used for auto-refreshing is not initialized, and so the cycle must always be an auto-refresh cycle.
276 ckio a13 or a11 a12 or a10 a11 to a2, or a9 to a2 csn wr ras casxx nn figure 11.32 synchronous dram mode write timing
277 11.3.6 pseudo-sram direct connection when the memory type bits (dramtp2-0) in bcr1 are set to 001, physical space area 3 becomes pseudo-sram and the pseudo-sram interface function that allows pseudo-sram to be connected directly to the sh7718r can be used. an interface data width of 16 or 32 bits can be selected. with directly connected pseudo-sram, the refresh signal and output enable signal are multiplexed. the signals used for connection are ce , oe / rfsh , we3 , we2 , we1 , and we0 . we3 and we2 are not used with a 16-bit data width. as access modes, burst access using the static column access function is supported in addition to ordinary read/write access. figure 11.33 shows an example of connection of 4m pseudo-srams with multiplexed oe and rfsh signals, using a 32-bit data width.
278 a18 a0 ce oe rfsh we a20 a2 ce we3 we2 we1 we0 n a18 a0 ce oe rfsh we a18 a0 ce oe rfsh we a18 a0 ce oe rfsh we figure 11.33 example of pseudo-sram connection (4m-bit devices)
279 basic timing: figure 11.34 shows the basic timing for pseudo-sram. tpc is the precharge cycle, and tr is the ce assert cycle. tc1 is the write data cycle, bs the assert cycle, and tc2 the read data latch cycle. tr tc1 tc2 (tpc) ckio a25 to a0 ce wr oe rfsh nn nn wen bs figure 11.34 basic access timing for pseudo-sram
280 wait state control: as the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. therefore, provision is made for state extension by using the setting bits in wcr2 and mcr. the timing with state extension using these settings is shown in figure 11.35. additional tpc cycles (cycles used to secure the ce precharge time) can be inserted by means of the tpc bits in mcr. the number of oe and wen assert cycles from ras assertion to cas assertion can be varied between 1 and 3 according to the setting of a3w1 and a3w0 in wcr2. trw cycles can be inserted by means of the rcd bits in mcr, and the number of cycles from ce assertion to bs assertion and write data output can be varied between 1 and 4.
281 ckio tr a25 to a0 ce wr oe rfsh nn nn wen bs figure 11.35 pseudo-sram wait state timing
282 burst access: in addition to the normal access mode in which ce is asserted and negated in each access, some pseudo-srams are provided with a static column mode for the case where consecutive accesses are made to the same row address. this mode allows fast access to data by keeping ce asserted and changing only the column address. normal access or burst access using static column mode can be selected by means of the burst enable (be) bit in mcr. the timing for burst access in static column mode is shown in figure 11.36. cycles can also be inserted by the wait state control function when burst access is performed.
283 ckio tr a25 to a4 a3 to a0 ce wr oe rfsh nn nn wen bs figure 11.36 pseudo-sram static column mode
284 refreshing: the bus state controller includes a function for controlling pseudo-sram refreshing. distributed refreshing by means of auto-refresh cycles can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr. refreshing is performed at intervals determined by the input clock selected by bits cks2?ks0 in rtcsr, and the value set in rtcor. the value of bits cks2?ks0 in rtcor should be set so as to satisfy the refresh interval stipulation for the pseudo-sram used. first set the rtcor, rtcnt, and the rmode and rfsh bits in mcr, then set the cks2?ks0. when the clock is selected by cks2?ks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. at the same time, rtcnt is cleared to zero and the count-up is restarted. figure 11.37 shows the auto-refresh cycle timing. the number of oe assert cycles for auto-refreshing is specified by the tras bits in mcr. the precharge time from oe negation until the next assertion of ce is determined by the setting of the tpc bits in mcr. auto-refreshing is performed in normal operation, in sleep mode, and in a manual reset. ckio trc ce oe rfsh figure 11.37 pseudo-sram auto-refreshing
285 with pseudo-sram, self-refresh mode is entered by holding the rfsh signal low for at least the prescribed time. self-refreshing is activated by setting both the rmode bit and the rfsh bit to 1. the self-refresh state is maintained while the cke signal is low. pseudo-sram cannot be accessed while in self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, access to pseudo-sram is disabled for the number of cycles specified by the tpc bits in mcr, but if the refresh reset time needed to return from self- refreshing is longer than this interval, coding must be provided to ensure that no access including auto-refresh?s made to pseudo-sram. self-refresh timing is shown in figure 11.38. settings must be made so that self-refresh clearing and data retention is performed correctly after self-refresh mode is cleared, and auto-refreshing is performed at the correct intervals. if the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of rtcnt. self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual reset. ckio trc ce oe rfsh figure 11.38 pseudo-sram self-refreshing power-on sequence: after powering pseudo-sram on, a minimum wait time of 100 ? is requested during which no access can be performed, followed by the prescribed number (usually 8 or more) of dummy auto-refresh cycles. as the bus state controller does not perform any special operations for a power-on reset, the power-on sequence must be carried out by the initialization program executed after a power-on reset.
286 11.3.7 burst rom interface setting bits a0bst (1,0), a5bst (1,0), and a6bst (1,0) in bcr1 to a non-zero value allows burst rom to be connected to areas 0, 5, and 6. the burst rom interface provides high-speed access to rom that has a nibble access function. the timing for nibble access to burst rom is shown in figure 11.39. two wait cycles are set. basically, access is performed in the same way as for normal space, but when the first cycle ends, the cs0 signal is not negated, and only the address is changed before the next access is executed. when 8-bit rom is connected, the number of consecutive accesses can be set as 4, 8, or 16 by bits a0bst (1,0), a5bst (1,0), or a6bst (1,0). when 16-bit rom is connected, 4 or 8 can be set in the same way. when 32-bit rom is connected, only 4 can be set. wait pin sampling is performed in the first access if one or more wait states are set, and is always performed in the second and subsequent accesses. the second and subsequent access cycles also comprise two cycles when a burst rom setting is made and the wait specification is 0. the timing in this case is shown in figure 11.40.
287 t1 tw tw tb2 tb1 tw tb2 ckio a25 to a4 a3 to a0 csn we rd nn bs wait nnnnnnnnnnnnn nnnnnnnn figure 11.39 burst rom wait access timing
288 t1 tb2 tb1 tb2 tb1 tb2 tb1 t2 ckio a25 to a4 a3 to a0 csn we rd nn bs wait nnnnnnnnnnnnn figure 11.40 burst rom basic access timing
289 11.3.8 pcmcia interface in the sh7718r, setting the a5pcm bit in bcr1 to 1 makes the bus interface for physical space area 5 an ic memory card interface as stipulated in jeida version 4.2 (pcmcia2.1). setting the a6pcm bit to 1 makes the bus interface for physical space area 6 an ic memory card and i/o card interface as stipulated in jeida version 4.2. when the ic memory card interface is selected, a bcr1 register setting enables page mode burst access mode to be used. this burst access mode is not stipulated in jeida version 4.2, but allows high-speed data access using rom provided with a burst mode, etc. when the pcmcia interface is used, a bus size of 8 or 16 bits can be set by bits a5sz1 and a5sz0, or a6sz1 and a6sz0, in bcr2. figure 11.41 shows an example of pcmcia card connection to the sh7718r. to enable active insertion of the pcmcia cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between the sh7718r? bus interface and the pcmcia cards. as operation in big-endian mode is not explicitly stipulated in the jeida/pcmcia specifications, the pcmcia interface for the sh7718r in big-endian mode is stipulated independently.
290 a24 to a0 d15 to d0 rd/ wr ce1b cs6 ce1a cs5 rd we1 iciord iciowr wait iois16 nn nn ce2 oe we pgm iord iowr wait iois16 n ce1 n g g g g nn nn nn nn ce2 oe we pgm wait n ce1 n g g g g nn nn ce2b ce2a figure 11.41 example of pcmcia interface
291 memory card interface basic timing: figure 11.42 shows the basic timing for the pcmcia ic memory card interface. when physical space areas 5 and 6 are designated as pcmcia interface areas, bus accesses are automatically performed as ic memory card interface accesses when the lower address 32 mbyte space of each area is accessed. with a high external bus frequency (ckio), the setup and hold times for the address (a24?0), card enable ( cs5 , ce2a , cs6 , ce2b ), and write data (d15?0) in a write cycle, become insufficient with respect to rd and wr (the we1 pin in the sh7718r). the sh7718r provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the pcr register. also, software waits by means of a wcr2 register setting and hardware waits by means of the wait pin can be inserted in the same way as for the basic interface. figure 11.43 shows the pcmcia memory bus wait timing.
292 ckio tpcm1 tpcm2 a25 to a0 cexx wr nn nn rd we1 bs figure 11.42 basic timing for pcmcia memory card interface
293 ckio tpcm0 a25 to a0 rd/ wr cexx nn nn bs wait figure 11.43 wait timing for pcmcia memory card interface
294 memory card interface burst timing: in the sh7718r, when the ic memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits a5bst1 and a5bst0 in bcr for physical space area 5, or bits a6bst1 and a6bst0 for area 6. this burst access mode is not stipulated in jeida version 4.2 (pcmcia2.1), but allows high-speed data access using rom provided with a burst mode, etc. burst access mode timing is shown in figures 11.44 and 11.45. ckio tpcm1 a25 to a4 cexx nn wr nn bs figure 11.44 basic timing for pcmcia memory card interface burst access
295 ckio tpcm0 a25 to a4 cexx nn wr nn bs wait figure 11.45 wait timing for pcmcia memory card interface burst access
296 when the entire 32-mbyte memory space is used as ic memory card interface space, the common memory/attribute memory switching signal reg is generated using a port, etc. if 16-mbytes or less of memory space is sufficient, using 16m bytes of memory space as common memory space and 16 mbytes as attribute memory space enables the a24 pin to be used for the reg signal. i/o space area 5: h'14000000 area 5: h'16000000 area 6: h'18000000 area 6: h'1a000000 area 5: h'14000000 area 5: h'15000000 h'16000000 area 6: h'18000000 area 6: h'19000000 area 6: h'1a000000 h'1b000000 attribute memory common memory attribute memory common memory i/o space up to 16-mbyte capacity (reg = a24) 32-mbyte capacity (reg = i/o port) common memory/ attribute memory common memory/ attribute memory figure 11.46 pcmcia space allocation
297 i/o card interface timing: figures 11.47 and 11.48 show the timing for the pcmcia i/o card interface. the i/o card interface is supported only for physical space area 6. switching between the i/o card interface and the ic memory card interface is performed according to the accessed address. when pcmcia is designated for physical space area 6, the bus access is automatically performed as an i/o card interface access when a physical address from h'1a000000 to h'1bffffff is accessed. when accessing a pcmcia i/o card, the access should be performed using a noncacheable area in virtual space (p2 or p3 space) or an area specified as noncacheable by the mmu. when an i/o card interface access is made to a pcmcia card in little-endian mode, dynamic sizing of the i/o bus width is possible using the iois16 pin. when a 16-bit bus width is set for area 6, if the iois16 signal is high during a word-size i/o bus cycle, the i/o port is recognized as being 8 bits in width. in this case, a data access for only 8 bits is performed in the i/o bus cycle being executed, followed automatically by a data access for the remaining 8 bits. figure 11.49 shows the basic timing for dynamic bus sizing. in big-endian mode, the iois16 signal is not supported, and is ignored. in big-endian mode, the iois16 signal should be fixed low.
298 ckio tpci1 tpci2 a25 to a0 rd/ wr cexx iciord nn iciowr nn bs figure 11.47 basic timing for pcmcia i/o card interface
299 ckio a25 to a0 rd/ wr cexx iciord iciowr nn nn bs wait iois16 figure 11.48 wait timing for pcmcia i/o card interface
300 ckio tpci0 a25 to a1 cexx wr iciord nn iciowr nn bs wait iois16 figure 11.49 dynamic bus sizing timing for pcmcia i/o card interface
301 11.3.9 waits between access cycles a problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with data in the next access. this results in lower reliability or incorrect operation. to avoid this problem, a data collision prevention feature has been provided. this memorizes the preceding access area and the kind of read/write. if there is a possibility of a bus collision when the next access is started, a wait cycle is inserted before the access cycle thus preventing a data collision. there are two cases in which a wait cycle is inserted: when an access is followed by an access to a different area, and when a read access is followed by a write access from the sh7718r. when the sh7718r performs consecutive write cycles, the data transfer direction is fixed (from the sh7718r to other memory) and there is no problem. with read accesses to the same area, in principle, data is output from the same data buffer, and wait cycle insertion is not performed. bits aniw1 and aniw0 (n = 0?) in wcr1 specify the number of idle cycles to be inserted between access cycles when a physical space area access is followed by an access to another area, or when the sh7718r performs a write access after a read access to physical space area n. if there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. waits are not inserted between accesses when bus arbitration is performed, since empty cycles are inserted for arbitration purposes.
302 t1 ckio csm csn nn bs wr rd nn nn nnnn nnnn nnn nnn figure 11.50 waits between access cycles 11.3.10 bus arbitration when a bus release request ( breq ) is received from an external device, buses are released after the bus cycle being executed is completed and a bus grant signal ( back ) is output . the bus is not released during burst transfers for cache fills. at the negation of breq , back is negated and bus use is restarted . see appendix b, pin states, for the pin status when the bus is released. the sh7718r sometimes needs to retrieve a bus it has released. for example, when memory generates a refresh request or an interrupt request internally, the sh7718r must perform the appropriate processing. the sh7718r has a bus request signal ( irqout ) for this purpose. when it must retrieve the bus, it asserts the irqout signal. devices asserting an external bus release request receive the assertion of the irqout signal and negate the breq signal to release the bus. the sh7718r retrieves the bus and carries out the processing. irqout pin assertion conditions: ? when a memory refresh request has been generated but the refresh cycle has not yet begun ? when an interrupt is generated with an interrupt request level higher than the setting of the interrupt mask bits (i3?0) in the status register (sr). (this does not depend on the sr.bl bit.)
303 11.4 usage notes 11.4.1 when area 6 is designated for pcmcia, with a 16-bit bus width in the case of consecutive word and byte accesses, or consecutive longword and byte accesses, in area 6, ce1b and ce2b are asserted simultaneously in the byte access. as a result, a byte write becomes a word-size write. in a byte read, the byte data at the specified address is read correctly. use one of the following methods to avoid this problem. 1. do not use area 6 pcmcia. 2. use an 8-bit bus width for area 6 pcmcia. 3. if a 16-bit bus width is used for area 6 pcmcia, do not perform byte-size write accesses. 4. in consecutive accesses a. and b. below a. word access byte access (write) b. longword access byte access (write) in which this problem arises, the problem can be avoided by performing a dummy read in a non-cacheable area as shown in (a') and (b') below. a'. word access dummy read byte access (write) b'. longword access dummy read byte access (write) 11.4.2 self-refreshing if the refresh mode bit (the rmode bit in registers mcr and dcr) is to be changed while the refresh control bit (the rfsh bit in registers mcr and dcr) is set to 1, use the procedure shown in a. and b. below. a. clear the refresh control bit to 0. b. when refreshing is not being performed, set the refresh control bit to 1 again and then change the refresh mode. 11.4.3 pcmcia area access if an sdram auto-refresh (cas-before-ras) request occurs during an area 6 pcmcia area access, cs6 is simultaneously asserted, in addition to the cs signal for the area to be accessed, when the auto-refresh is performed. if the following specifications are made, cs3 and cs6 will be asserted simultaneously: area 3: sdram area 6: pcmcia
304 cs6 remains asserted until the end of the following pcmcia bus cycle. pcmcia area cs (cs6) asserted pcmcia cycle cs (cs3) asserted in cas-before-ras refresh auto-refresh cycle ckio cs3 ras bs cs6 restrictions: when using pcmcia in area 6 and also using sdram, the area 6 cs signal (cs6) may be asserted earlier than usual, at the same time as the preceding auto-refresh cycle. remedy: this anomaly occurs only in area 6. there is no problem with area 5. therefore, if use of both sdram and pcmcia in the system is being considered, area 5 should be used. if area 6 is used, the system design should allow for cs to be asserted early without causing any problems.
305 section 12 timer (tmu) 12.1 overview the sh7718r uses a three-channel 32-bit timer unit (tmu). 12.1.1 features the tmu has the following features: ? each channel is provided with an auto-reload 32-bit down counter ? channel 2 is provided with an input capture function ? all channels are provided with 32-bit constant registers and 32-bit down counters that can be read or written to at any time ? all channels generate interrupt requests when the 32-bit down counter underflows (h'00000000 h'ffffffff) ? allows selection between 6 counter input clocks: external clock (tclk), on-chip rtc output clock (16 khz), p?4, p?16, p?64, p?256. (p?is the internal clock for peripheral modules and can be selected as 1/4, 1/2, or the same frequency as that of the cpu operating clock ?) see section 10, on-chip oscillation circuits, for more information on the clock pulse generator. ? all channels can operate when the sh7718r is in standby mode: when the rtc output clock is being used as the counter input clock, the sh7718r is still able to count in standby mode. ? synchronized read: tcnt is a sequentially changing 32-bit register. since the peripheral module used has an internal bus width of 16 bits, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. to correct the discrepancy in the counter read value caused by this time lag, a synchronization circuit is built into the tcnt so that the entire 32-bit data in the tcnt can be read at once. ? the maximum operating frequency of the 32-bit counter is 2 mhz on all channels: operate the sh7718r so that the clock input to the timer counters of each channel (obtained by dividing the external clock and internal clock with the prescaler) does not exceed the maximum operating frequency. 12.1.2 block diagram figure 12.1 shows a block diagram of the tmu.
306 tocr prescaler tstr tcr0 tcnt0 module bus internal bus tcor0 tcr1 tcnt1 tcor1 counter controller tclk p rtcclk tuni0 bus interface ch. 0 interrupt controller interrupt controller interrupt controller counter controller counter controller tuni1 tuni2 ticpi2 tcr2 tcpr2 tcnt2 tcor2 tmu ch. 1 ch. 2 clock controller tocr: tstr: tcr: timer output control register timer start register tcnt: tcor: tcpr2: 32-bit timer counter 32-bit timer constant register 32-bit input capture register timer control register figure 12.1 tmu block diagram
307 12.1.3 pin configuration table 12.1 shows the pin configuration of the tmu. table 12.1 pin configuration channel pin i/o description clock input/clock output tclk i/o external clock input pin/input capture control input pin/realtime clock (rtc) output pin 12.1.4 register configuration table 12.2 shows the tmu register configuration. table 12.2 tmu register configuration channel register abbreviation r/w initial value address access size common timer output control register tocr r/w h'00 h'fffffe90 8 timer start register tstr r/w h'00 h'fffffe92 8 0 timer constant register 0 tcor0 r/w h'ffffffff h'fffffe94 32 timer counter 0 tcnt0 r/w h'ffffffff h'fffffe98 32 timer control register 0 tcr0 r/w h'0000 h'fffffe9c 16 1 timer constant register 1 tcor1 r/w h'ffffffff h'fffffea0 32 timer counter 1 tcnt1 r/w h'ffffffff h'fffffea4 32 timer control register 1 tcr1 r/w h'0000 h'fffffea8 16 2 timer constant register 2 tcor2 r/w h'ffffffff h'fffffeac 32 timer counter 2 tcnt2 r/w h'ffffffff h'fffffeb0 32 timer control register 2 tcr2 r/w h'0000 h'fffffeb4 16 input capture register 2 tcpr2 r/w undefined h'fffffeb8 32
308 12.2 tmu registers 12.2.1 timer output control register (tocr) tocr is an 8-bit read/write register that selects whether to use the external tclk pin as an external clock or an input capture control usage input pin, or an output pin for the on-chip rtc output clock. tocr is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: tcoe initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bits 7 to 1?eserved: these bits are always read as 0. the write value should always be 0. bit 0?imer clock pin control (tcoe): selects use of the timer clock pin (tclk) as an external clock input pin or input pin for input capture control for the on-chip timer, or as an output pin for the on-chip rtc output clock. bit 0: tcoe description 0 timer clock pin (tclk) used as external clock input or input capture control input pin for the on-chip timer (initial value) 1 timer clock pin (tclk) used as output pin for on-chip rtc output clock
309 12.2.2 timer start register (tstr) tstr is an 8-bit read/write register that selects whether to run or halt the timer counters (tcnt) for channels 0?. tstr is initialized to h'00 by a power-on reset or manual reset. in standby mode, when the pll1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the mstp2 bit is set to 1 in stbcr, tstr is initialized only when the input clock selected for the channel is an external clock (tclk) or the peripheral clock (p?. bit: 7 6 5 4 3 2 1 0 bit name: str2 str1 str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bits 7 to 3?eserved: these bits are always read as 0. the write value should always be 0. bit 2?ounter start 2 (str2): selects whether to run or halt timer counter 2 (tcnt2). bit 2: str2 description 0 halt tcnt2 count (initial value) 1 start tcnt2 counting bit 1?ounter start 1 (str1): selects whether to run or halt timer counter 1 (tcnt1). bit 1: str1 description 0 halt tcnt1 count (initial value) 1 start tcnt1 counting bit 0?ounter start 0 (str0): selects whether to run or halt timer counter 0 (tcnt0). bit 0: str0 description 0 halt tcnt0 count (initial value) 1 start tcnt0 counting
310 12.2.3 timer control register (tcr) the timer control registers (tcr) control the timer counters (tcnt) and interrupts. the tmu has three tcr, registers one for each channel. the tcr registers are 16-bit read/write registers that control the issuance of interrupts when the flag indicating timer counter (tcnt) underflow has been set to 1, and also carry out counter clock selection. when the external clock has been selected, they also select its edge. additionally, tcr2 controls the channel 2 input capture function and the issuance of interrupts during input capture. the tcrs are initialized to h'0000 by a power-on reset and manual reset. in standby mode, when the pll1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the mstp2 bit is set to 1 in stbcr, the tcrs retain their contents when the input clock selected for the channel is an external clock (tclk) or the peripheral clock (p?, and continue operating when the selected clock is the on-chip rtc output clock (rtcclk). channel 0 and 1 tcr bit configuration: bit: 15 14 13 12 11 10 9 8 bit name: unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 bit name: unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w channel 2 tcr bit configuration: bit: 15 14 13 12 11 10 9 8 bit name: icpf unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: icpe1 icpe0 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
311 bits 15 to 10, 9 (except tcr2), 7, and 6 (except tcr2)?eserved: these bits are always read as 0. the write value should always be 0. bit 9?nput capture interrupt flag (icpf): a function of channel 2 only: the flag is set when input capture is requested via the tclk pin. bit 9: icpf description 0 no input capture request has been issued. clearing condition: when 0 is written to icpf (initial value) 1 input capture has been requested via the tclk pin. setting condition: when an input capture is requested via the tclk pin* note: * contents do not change when 1 is written to icpf. bit 8?nderflow flag (unf): status flag that indicates occurrence of a tcnt underflow. bit 8: unf description 0 tcnt has not underflowed. clearing condition: when 0 is written to unf (initial value) 1 tcnt has underflowed (h'00000000 h'ffffffff). setting condition: when tcnt underflows* note: * contents do not change when 1 is written to unf. bits 7 and 6?nput capture control (icpe1, icpe0): a function of channel 2 only: determines whether the input capture function can be used, and when used, whether or not to enable interrupts. when using this input capture function it is necessary to set the tclk pin to input mode with the tcoe bit in the tocr register. additionally, use the ckeg bit to designate use of either the rising or falling edge of the tclk pin to set the value in tnct2 in the input capture register (tcpr2). bit 7: icpe1 bit 6: icpe0 description 0 0 input capture function is not used. (initial value) 1 reserved (cannot be set) 1 0 input capture function is used. interrupts due to icpf are not enabled. 1 input capture function is used. interrupts due to icpf are enabled.
312 bit 5?nderflow interrupt control (unie): controls enableing of interrupt generation when the status flag (unf) indicating tcnt underflow has been set to 1. bit 5: unie description 0 interrupts due to unf are not enabled. (initial value) 1 interrupts due to unf are enabled. bits 4 and 3?lock edge 1, 0 (ckeg1, ckeg0): these bits select the external clock edge when the external clock is selected, or when the input capture function is used. bit 4: ckeg1 bit 3: ckeg0 description 0 0 count/capture register set on rising edge (initial value) 1 count/capture register set on falling edge 1 count/capture register set on both rising and falling edge bits 2 to 0?imer prescalers 2? (tpsc2?psc0): these bits select the tcnt count clock. bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 internal clock: count on p /4 (initial value) 1 internal clock: count on p /16 1 0 internal clock: count on p /64 1 internal clock: count on p /256 1 0 0 internal clock: count on clock output of on-chip rtc (rtcclk) 1 external clock: count on tclk pin input 1 0 reserved 1 reserved
313 12.2.4 timer constant register (tcor) the timer constant registers are 32-bit registers. the tmu has three tcor registers, one for each of the three channels. tcor is a 32-bit read/write register. when a tcnt count-down results in an underflow, the tcor value is set in tcnt and the count-down continues from that value. tcor is initialized to h'ffffffff by a power-on reset or manual reset; it is not initialized in standby mode, and retains its contents. tcor: bit: 31 30 29 28 27 26 25 24 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 12.2.5 timer counters (tcnt) the timer counters are 32-bit read/write registers. the tmu has three timer counters, one for each channel. tcnt counts down upon input of a clock. the clock input is selected using the tpsc2?psc0 bits in the timer control register (tcr).
314 when a tcnt count-down results in an underflow (h'00000000 h'ffffffff), the underflow flag (unf) in the timer control register (tcr) of the relevant channel is set. the tcor value is simultaneously set in tcnt itself and the count-down continues from that value. because the internal bus for the sh7718r on-chip supporting modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. since tcnt counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves. to correct the discrepancy, a buffer register is connected to tcnt so that upper and lower halves are not read separately. the entire 32-bit data in tcnt can thus be read at once. tcnt is initialized to h'ffffffff by a power-on reset or manual reset. in standby mode, when the pll1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the mstp2 bit is set to 1 in stbcr, tcnt retains its contents when the input clock selected for the channel is an external clock (tclk) or the peripheral clock (p?, and continues operating when the selected clock is the on-chip rtc output clock (rtcclk). tcnt: bit: 31 30 29 28 27 26 25 24 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
315 12.2.6 input capture register (tcpr2) the input capture register (tcpr2) is a read-only 32-bit register built only into timer 2. control of tcpr2 setting conditions due to the tclk pin is affected by the input capture function bits (icpe1/icpe2 and ckeg1/ckeg0)) in tcr2. when a tcpr2 setting indication due to the tclk pin occurs, the value of tcnt2 is copied into tcpr2. tcnt2 is not initialized by a power-on reset or manual reset, or in standby mode. tcpr2: bit: 31 30 29 28 27 26 25 24 bit name: initial value: r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 bit name: initial value: r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 bit name: initial value: r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 bit name: initial value: r/w: r r r r r r r r
316 12.3 tmu operation 12.3.1 overview each of the three channels has a 32-bit timer counter (tcnt) and a 32-bit timer constant register. the tcnt counts down. the auto-reload function enables synchronized counting and counting by external events. channel 2 has an input capture function. 12.3.2 basic functions counter operation: when the str0?tr2 bits in the timer start register (tstr) are set, the corresponding timer counter (tcnt) starts counting. when a tcnt underflows (h'00000000 h'ffffffff), the unf flag of the corresponding timer control register (tcr) is set. at this time, if the unie bit in tcr is 1, an interrupt request is sent to the cpu. also at this time, the value is copied from tcor to tcnt and the down-count operation is continued. the count operation is set as follows (figure 12.2): 1. select the counter clock with the tpsc2?psc0 bits in the timer control register (tcr). if the external clock is selected, set the tclk pin to input mode with the toce bit in tocr, and select its edge with the ckeg1 and ckeg0 bits in tcr. 2. use the unie bit in tcr to set whether to generate an interrupt when tcnt underflows. 3. when using the input capture function, set the icpe bits in tcr, including the choice of whether or not to use the interrupt function (channel 2 only). 4. set a value in the timer constant register (tcor) (the cycle is the set value plus 1). 5. set the initial value in the timer counter (tcnt). 6. set the str bit in the timer start register (tstr) to 1 to start operation.
317 operation selection select counter clock set underflow interrupt generation set timer constant register initialize timer counter start counting (1) (2) (4) (5) (6) set interrupt generation when using input capture function (3) note: when an interrupt has been generated, clear the flag in the interrupt handler that caused it. if interrupts are enabled without clearing the flag, another interrupt will be generated. figure 12.2 setting the count operation
318 auto-reload count operation: figure 12.3 shows the tcnt auto-reload operation. tcnt value tcor h'00000000 str0 str2 unf tcor value set to tcnt during underflow time figure 12.3 auto-reload count operation tcnt count timing: ? internal clock operation: set the tpsc2?psc0 bits in tcr to select whether peripheral module clock p?or one of the four internal clocks created by dividing it is used (p?4, p?16, p?64, p?256). figure 12.4 shows the timing. p internal clock tcnt input clock tcnt n + 1 n n 1 figure 12.4 count timing when internal clock is operating ? external clock operation: set the tpsc2?psc0 bits in tcr to select the external clock (tclk) as the timer clock. use the ckeg1 and ckeg0 bits in tcr to select the detection edge. rise, fall or both may be selected. the pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges. a shorter pulse width will result in accurate operation. figure 12.5 shows the timing for both-edge detection.
319 p external clock input pin tcnt input clock tcnt n + 1 n n 1 figure 12.5 count timing when external clock is operating (both edges detected) ? on-chip rtc clock operation: set the tpsc2?psc0 bits in tcr to select the on-chip rtc clock as the timer clock. figure 12.6 shows the timing. rtc output clock tcnt tcnt input clock n + 1 n n 1 figure 12.6 count timing when on-chip rtc clock is operating input capture function: channel 2 has an input capture function (figure 12.7). when using the input capture function, set the tclk pin to input mode with the tcoe bit in the timer output control register (tocr) and set the timer operation clock to internal clock or on-chip rtc clock with the tpcs2?pcs0 bits in the timer control register (tcr). also, designate use of the input capture function and whether to generate interrupts on using it with the ipce1?pce0 bits in tcr, and designate the use of either the rising or falling edge of the tclk pin to set the timer counter (tnct) value into the input capture register (tcpr) with the ckeg1?keg0 bits in tcr. the input capture function cannot be used in standby mode.
320 tcnt value tcor h'00000000 tclk tcpr2 set tcnt value icpi tcor value set to tcnt during underflow time figure 12.7 operation timing when using the input capture function (using tclk rising edge) 12.4 interrupts there are two sources of tmu interrupts: underflow interrupts and interrupts when using the input capture function. 12.4.1 status flag set timing unf is set to 1 when the tcnt underflows. figure 12.8 shows the timing. p tcnt underflow signal unf tuni tcor value h'00000000 figure 12.8 unf set timing
321 12.4.2 status flag clear timing the status flag can be cleared by writing a 0 from the cpu. figure 12.9 shows the timing. p peripheral address bus unf tcr address t1 t2 tcr write cycle t3 figure 12.9 status flag clear timing 12.4.3 interrupt sources and priorities the tmu produces underflow interrupts for each channel. when the interrupt request flag and interrupt enable bit are both set to 1, the interrupt is requested. codes are set in the exception source register (intevt) for these interrupts and interrupt handling occurs according to the codes. the relative priorities of channels can be changed using the interrupt controller (see section 6, interrupt controller). table 12.3 lists tmu interrupt sources. table 12.3 tmu interrupt sources channel interrupt source description priority 0 tuni0 underflow interrupt 0 high 1 tuni1 underflow interrupt 1 2 tuni2 underflow interrupt 2 ticpi2 input capture interrupt 2 low
322 12.5 usage notes 12.5.1 writing to registers synchronization processing is not performed for timer counting during register writes. when writing to registers, always clear the appropriate start bits for the channel (str2?tr0) in the timer start register (tstr) to halt timer counting. 12.5.2 reading registers synchronization processing is performed for timer counting during register reads. when timer counting and register read processing are performed simultaneously, the register value before tcnt counting down (with synchronization processing) is read.
323 section 13 realtime clock (rtc) 13.1 overview the sh7718r has a realtime clock (rtc) with its own 32.768-khz crystal oscillator. 13.1.1 features ? clock and calendar functions (bcd display): seconds, minutes, hours, date, day of the week, month, and year ? 1-hz to 64-hz timer (binary display) ? start/stop function ? 30-second adjust function ? alarm interrupt: frame comparison of seconds, minutes, hours, date, day of the week, and month can be used as conditions for the alarm interrupt ? cyclic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds ? carry interrupt: a carry interrupt indicates when a carry occurs during a counter read ? automatic leap year correction 13.1.2 block diagram the following abbreviations are used in the block diagram of the rtc (figure 13.1): r64cnt: 64-hz counter rsecar: second alarm register rseccnt: second counter rminar: minute alarm register rmincnt: minute counter rhrar: hour alarm register rhrcnt: hour counter rwkar: day of the week alarm register rwkcnt: day of the week counter rdayar: date alarm register rdaycnt: date counter rmonar: month alarm register rmoncnt: month counter rcr1: rtc control register 1 ryrcnt: year counter rcr2: rtc control register 2
324 module bus rtc internal bus interrupt control circuit prescaler ( 2) rtcclk bus interface carry detection circuit ati pri cui r64cnt reset rseccnt rmincnt rhrcnt rwkcnt 16.384 khz rdaycnt rmoncnt ryrcnt comparator rsecar rminar rhrar rwkar rdayar rcr1 rcr2 30- second adj extal2 32.768 khz 128 hz xtal2 externally connected circuit oscillator circuit prescaler ( 128) rmonar figure 13.1 rtc block diagram
325 13.1.3 pin configuration table 13.1 shows the rtc pin configuration. table 13.1 rtc pin configuration pin abbreviation i/o description rtc oscillator crystal pin extal2 i connects crystal to rtc oscillator rtc oscillator crystal pin xtal2 o connects crystal to rtc oscillator clock input/clock output tclk i/o external clock input pin/input capture control input pin/realtime clock (rtc) output pin (shared by tmu) dedicated power-supply pin for rtc v cc (rtc) dedicated power-supply pin for rtc* dedicated gnd pin for rtc v ss (rtc) dedicated gnd pin for rtc* note: except in hardware standby mode, connect all v cc and v ss pins to the system power supply (power should be supplied constantly). in hardware standby mode, power should be supplied at least to v cc (rtc) and v ss (rtc). if power is not supplied to v cc and v ss pins other than v cc (rtc) and v ss (rtc), hold the ca pin low.
326 13.1.4 rtc register configuration table 13.2 shows the rtc register configuration. table 13.2 rtc registers name abbreviation r/w initial value address access size 64-hz counter r64cnt r undefined h'fffffec0 8 second counter rseccnt r/w undefined h'fffffec2 8 minute counter rmincnt r/w undefined h'fffffec4 8 hour counter rhrcnt r/w undefined h'fffffec6 8 day of week counter rwkcnt r/w undefined h'fffffec8 8 date counter rdaycnt r/w undefined h'fffffeca 8 month counter rmoncnt r/w undefined h'fffffecc 8 year counter ryrcnt r/w undefined h'fffffece 8 second alarm register rsecar r/w undefined* h'fffffed0 8 minute alarm register rminar r/w undefined* h'fffffed2 8 hour alarm register rhrar r/w undefined* h'fffffed4 8 day of week alarm register rwkar r/w undefined* h'fffffed6 8 date alarm register rdayar r/w undefined* h'fffffed8 8 month alarm register rmonar r/w undefined* h'fffffeda 8 rtc control register 1 rcr1 r/w h'00 h'fffffedc 8 rtc control register 2 rcr2 r/w h'09 h'fffffede 8 note: * only the enb bits of each register are initialized. 13.2 rtc registers 13.2.1 64-hz counter (r64cnt) the 64-hz counter (r64cnt) is an 8-bit read-only register that indicates the status of the rtc divider circuit between 64 hz and 1 hz. r64cnt is reset to h'00 by setting the reset bit in rtc control register 2 (rcr2) or the adj bit in rcr2 to 1.
327 r64cnt is not initialized by a power-on reset or manual reset, or in standby mode. bit 7 always reads 0. bit: 7 6 5 4 3 2 1 0 bit name: 1hz 2hz 4hz 8hz 16hz 32hz 64hz initial value: 0 r/w: r r r r r r r r 13.2.2 second counter (rseccnt) the second counter (rseccnt) is an 8-bit read/write register used for setting/counting in the bcd-coded second section of the rtc. the count operation is performed by a carry for each second of the 64 hz counter. the range that can be set is 00?9 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rseccnt is not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: 10 seconds 1 second initial value: 0 r/w: r r/w r/w r/w r/w r/w r/w r/w 13.2.3 minute counter (rmincnt) the minute counter (rmincnt) is an 8-bit read/write register used for setting/counting in the bcd-coded minute section of the rtc. the count operation is performed by a carry for each minute of the second counter. the range that can be set is 00?9 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rmincnt is not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: 10 minutes 1 minute initial value: 0 r/w: r r/w r/w r/w r/w r/w r/w r/w
328 13.2.4 hour counter (rhrcnt) the hour counter (rhrcnt) is an 8-bit read/write register used for setting/counting in the bcd- coded hour section of the rtc. the count operation is performed by a carry for each 1 hour of the minute counter. the range that can be set is 00?3 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rhrcnt is not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: 10 hours 1 hour initial value: 0 0 r/w: r r r/w r/w r/w r/w r/w r/w 13.2.5 day of the week counter (rwkcnt) the day of the week counter (rwkcnt) is an 8-bit read/write register used for setting/counting in the bcd-coded day of week section of the rtc. the count operation is performed by a carry for each day of the date counter. the range that can be set is 0? (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rwkcnt is not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: day of week initial value: 0 0 0 0 0 r/w: r r r r r r/w r/w r/w
329 days of the week are coded as shown in table 13.3. table 13.3 day-of-week codes (rwkcnt) day of week code sunday 0 monday 1 tuesday 2 wednesday 3 thursday 4 friday 5 saturday 6 13.2.6 date counter (rdaycnt) the date counter (rdaycnt) is an 8-bit read/write register used for setting/counting in the bcd- coded date section of the rtc. the count operation is performed by a carry for each day of the hour counter. the range that can be set is 01?1 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rdaycnt is not initialized by a power-on reset or manual reset, or in standby mode. the rdaycnt range that can be set changes with each month and in leap years. please confirm the correct setting. bit: 7 6 5 4 3 2 1 0 bit name: 10 days 1 day initial value: 0 0 r/w: r r r/w r/w r/w r/w r/w r/w
330 13.2.7 month counter (rmoncnt) the month counter (rmoncnt) is an 8-bit read/write register used for setting/counting in the bcd-coded month section of the rtc. the count operation is performed by a carry for each month of the date counter. the range that can be set is 00?2 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. rmoncnt is not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: 10 months 1 month initial value: 0 0 0 r/w: r r r r/w r/w r/w r/w r/w 13.2.8 year counter (ryrcnt) the year counter (ryrcnt) is an 8-bit read/write register used for setting/counting in the bcd- coded year section of the rtc. the least significant 2 digits of the western calendar year are displayed. the count operation is performed by a carry for each year of the month counter. the range that can be set is 00?9 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2. ryrcnt is not initialized by a power-on reset or manual reset, or in standby mode. leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result of 0. bit: 7 6 5 4 3 2 1 0 bit name: 10 years 1 year initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w
331 13.2.9 second alarm register (rsecar) the second alarm register (rsecar) is an 8-bit read/write register, and an alarm register corresponding to the bcd-coded second section counter rseccnt of the rtc. when the enb bit is set to 1, a comparison with the rseccnt value is performed. from among the rsecar/rminar/rhrar/rwkar/rdayar/rmonar registers, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 00?9 (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rsecar is initialized to 0 by a power-on reset. the remaining rsecar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: enb 10 seconds 1 second initial value: 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 13.2.10 minute alarm register (rminar) the minute alarm register (rminar) is an 8-bit read/write register, and an alarm register corresponding to the bcd-coded minute section counter rmincnt of the rtc. when the enb bit is set to 1, a comparison with the rmincnt value is performed. from among the rsecar/rminar/rhrar/rwkar/rdayar/rmonar registers, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 00?9 (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rminar is initialized by a power-on reset. the remaining rminar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: enb 10 minutes 1 minute initial value: 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
332 13.2.11 hour alarm register (rhrar) the hour alarm register (rhrar) is an 8-bit read/write register, and an alarm register corresponding to the bcd-coded hour section counter rhrcnt of the rtc. when the enb bit is set to 1, a comparison with the rhrcnt value is performed. from among the rsecar/rminar/rhrar/rwkar/rdayar/rmonar registers, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 00?3 (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rhrar is initialized by a power-on reset. the remaining rhrar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: enb 10 hours 1 hour initial value: 0 0 r/w: r/w r r/w r/w r/w r/w r/w r/w 13.2.12 day of the week alarm register (rwkar) the day of the week alarm register (rwkar) is an 8-bit read/write register, and an alarm register corresponding to the bcd-coded day of week section counter rwkcnt of the rtc. when the enb bit is set to 1, a comparison with the rwkcnt value is performed. from among the rsecar/rminar/rhrar/rwkar/rdayar/rmonar registers, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 0? (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rwkar is initialized by a power-on reset. the remaining rwkar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: enb day of week initial value: 0 0 0 0 0 r/w: r/w r r r r r/w r/w r/w
333 days of the week are coded as shown in table 13.4. table 13.4 day-of-week codes (rwkar) day of week code sunday 0 monday 1 tuesday 2 wednesday 3 thursday 4 friday 5 saturday 6 13.2.13 date alarm register (rdayar) the date alarm register (rdayar) is an 8-bit read/write register, and an alarm register corresponding to the bcd-coded date section counter rdaycnt of the rtc. when the enb bit is set to 1, a comparison with the rdaycnt value is performed. from among the registers rsecar, rminar, rhrar, rwkar, rdayar, rmonar, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 01?1 (decimal) + enb bit. errant operation will result if any other value is set. the rdaycnt range that can be set changes with some months and in leap years. please confirm the correct setting. the enb bit in rdayar is initialized by a power-on reset. the remaining rdayar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: enb 10 days 1 day initial value: 0 0 r/w: r/w r r/w r/w r/w r/w r/w r/w
334 13.2.14 month alarm register (rmonar) the month alarm register (rmonar) is an 8-bit read/write register, and an alarm register corresponding to the bcd-coded month section counter rmoncnt of the rtc. when the enb bit is set to 1, a comparison with the rmoncnt value is performed. from among the registers rsecar, rminar, rhrar, rwkar, rdayar, rmonar, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an rtc alarm interrupt is generated. the range that can be set is 01?2 (decimal) + enb bit. errant operation will result if any other value is set. the enb bit in rmonar is initialized by a power-on reset. the remaining rmonar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: enb 10 months 1 month initial value: 0 0 0 r/w: r/w r r r/w r/w r/w r/w r/w 13.2.15 rtc control register 1 (rcr1) the rtc control register 1 (rcr1) is an 8-bit read/write register that affects carry flags and alarm flags. it also selects whether to generate interrupts for each flag. because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. rcr1 is initialized to h'00 by a power-on reset. in a manual reset, all bits are initialized to 0 except for the cf flag, which is undefined. when using the cf flag, it must be initialized beforehand. this register is not initialized in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: cf cie aie af initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r/w r/w r r r/w
335 bit 7?arry flag (cf): status flag that indicates that a carry has occurred. cf is set to 1 when a count-up to r64cnt or rseccnt occurs. a count register value read at this time cannot be guaranteed; another read is required. bit 7: cf description 0 no count up of r64cnt or rseccnt. clearing condition: when 0 is written to cf (initial value) 1 count up of r64cnt or rseccnt. setting condition: when 1 is written to cf bits 6, 5, 2, and 1?eserved: these bits always read 0. the write value should always be 0. bit 4?arry interrupt enable flag (cie): when the carry flag (cf) is set to 1, the cie bit enables interrupts. bit 4: cie description 0 a carry interrupt is not generated when the cf flag is set to 1 (initial value) 1 a carry interrupt is generated when the cf flag is set to 1 bit 3?larm interrupt enable flag (aie): when the alarm flag (af) is set to 1, the aie bit allows interrupts. bit 3: aie description 0 an alarm interrupt is not generated when the af flag is set to 1 (initial value) 1 an alarm interrupt is generated when the af flag is set to 1 bit 0?larm flag (af): the af flag is set to 1 when the alarm time set in an alarm register (only registers with enb bit set to 1) matches the clock and calendar time. bit 0: af description 0 clock/counter and alarm register have not matched since last reset to 0. clearing condition: when 0 is written to af (initial value) 1 setting condition: clock/counter and alarm register have matched (only registers with enb set)* note: * contents do not change when 1 is written to af.
336 13.2.16 rtc control register 2 (rcr2) the rtc control register 2 (rcr2) is an 8-bit read/write register for periodic interrupt control, 30- second adjustment adj, divider circuit reset, and rtc count start/stop control. it is initialized to h'09 by a power-on reset. it is not initialized by a manual reset or in standby mode, and retains its contents. bit: 7 6 5 4 3 2 1 0 bit name: pef pes2 pes1 pes0 rtcen adj reset start initial value: 0 0 0 0 1 0 0 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?eriodic interrupt flag (pef): indicates interrupt generation with the period designated by the pes bits. when set to 1, pef generates periodic interrupts. bit 7: pef description 0 interrupts not generated with the period designated by the pes bits. clearing condition: when 0 is written to pef (initial value) 1 interrupts generated with the period designated by the pes bits. setting condition: when 1 is written to pef bits 6??eriodic interrupt flags (pes2?es0): these bits specify the periodic interrupt. bit 6: pes2 bit 5: pes1 bit 4: pes0 description 0 0 0 no periodic interrupts generated (initial value) 1 periodic interrupt generated every 1/256 second 1 0 periodic interrupt generated every 1/64 second 1 periodic interrupt generated every 1/16 second 1 0 0 periodic interrupt generated every 1/4 second 1 periodic interrupt generated every 1/2 second 1 0 periodic interrupt generated every 1 second 1 periodic interrupt generated every 2 seconds bit 3?tcen: controls the operation of the crystal oscillator for the rtc. bit 3: rtcen description 0 halts the crystal oscillator for the rtc. 1 runs the crystal oscillator for the rtc. (initial value)
337 bit 2?0-second adjustment (adj): when 1 is written to the adj bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. the divider circuit will be simultaneously reset. this bit always reads 0. bit 2: adj description 0 runs normally. (initial value) 1 (write) 30-second adjustment. bit 1?eset (reset): when 1 is written, initializes the divider circuit. this bit always reads 0. bit 1: reset description 0 runs normally. (initial value) 1 (write) divider circuit is reset. bit 0?tart bit (start): halts and restarts the counter (clock). bit 0: start description 0 second/minute/hour/day/week/month/year counter halts. 1 second/minute/hour/day/week/month/year counter runs normally. (initial value) note: the 64-hz counter always runs unless stopped with the rtcen bit. 13.3 rtc operation 13.3.1 initial settings of registers after power-on all the registers should be set after the power is turned on. 13.3.2 setting the time part (a) in figure 13.2 shows how to set the time when the clock is stopped. this works when the entire calendar or clock is to be set. part (b) in figure 13.2 describes how to set the clock when the clock is running. this works when only part of the calendar or clock needs to be reset (e.g., changing only the seconds or only the hour). the write status is checked using the carry flags. when there is a carry during the writing of new data, the new data is automatically updated. since this causes errors in the data, the data must be rewritten if the carry flag is set to 1. the interrupt function can be used to determine the status of the carry flag.
338 write 1 to reset and 0 to start in the rcr2 register order is irrelevant write 1 to start in the rcr2 register set seconds, minutes, hour, day, day of the week, month and year read rcr1 and check cf carry flag = 1? no yes stop clock, reset divider circuit a. to reset the divider circuit and set the counter b. to set the seconds-year counter start clock clear the carry flag write the counter register write 0 to cf in rcr1 note: set af to 1 so that alarm flag is not cleared figure 13.2 setting the time
339 13.3.3 reading the time figure 13.3 shows how to read the time. if a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. part (a) in figure 13.3 shows the method of reading the time without using interrupts; part (b) in figure 13.3 shows the method using carry interrupts. to keep programming simple, method (a) should normally be used. write 0 to cf in rcr1 note: set af to 1 so that alarm flag is not cleared. read rcr1 and check cf write 0 to cie in rcr1 carry flag = 1? no yes clear the carry flag disable the carry interrupt read counter register write 1 to cie in rcr1, and write 0 to cf in rcr1 note: set af in rcr1 to 1 so that alarm flag is not cleared. interrupt generated? no yes enable the carry interrupt clear the carry flag disable the carry interrupt read counter register to read the time without using interrupts b. to use interrupts a. figure 13.3 reading the time
340 13.3.4 alarm function figure 13.4 shows how to use the alarm function. alarms can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. set the enb bit (bit 7) in the register on which the alarm is placed to 1, and then set the alarm time in the lower bits. clear the enb bit in the register on which the alarm is placed to 0. when the clock and alarm times match, a 1 is set in the af bit (bit 0) in rcr1. alarm detection can be checked by reading this bit, but normally it is done by interrupt. if 1 is placed in the aie bit (bit 3) in rcr1, an interrupt is generated when an alarm occurs. when using interrupts, the interrupt enable bit (bit 3 of rcr1) is 1 clock running set alarm time set whether to use alarm interrupt always set, since the flag may have been set while the alarm time was being set. write 0 to bit 0 of rcr1 to clear it. clear alarm flag monitor alarm time (wait for interrupt or check alarm flag) figure 13.4 using the alarm function
341 13.3.5 crystal resonator circuit crystal resonator circuit constants (recommended values) are shown in table 13.5, and the rtc crystal resonator circuit in figure 13.5. table 13.5 recommended resonator circuit constants (recommended values) fosc cin cout 32.768 khz 10 to 22 pf 10 to 22 pf sh7718r extal2 xtal2 xtal c in c out r f r d notes : 1. select either the cin or cout side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. built-in resistance value rf (typ. value) = 10 m ? , rd (typ. value) = 400 k ? 3. cin and cout values include floating capacitance due to the wiring. take care when using a solid-earth board. 4. the crystal resonator stabilization time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. place the crystal resonator and load capacitors cin and cout as close as possible to the chip. (correct oscillation may not be possible if there is externally induced noise in the extal2 and xtal2 pins.) 6. ensure that the crystal resonator connection pin (extal2 and xtal2) wiring is routed as far away as possible from other power lines (except gnd) and signal lines. figure 13.5 example of crystal resonator circuit connection
342 13.4 usage notes 13.4.1 register writes during rtc count the following rtc registers cannot be written to while the rtc is counting (bit 0 of rcr2 = 1): rseccnt, rmincnt, rhrcnt, rdaycnt, rwkcnt, rmoncnt, ryrcnt the rtc count must be stopped before writing to any of these registers.
343 section 14 serial communication interface (sci) 14.1 overview the sh7718r has an on-chip serial communication interface (sci) that supports both asynchronous and synchronous serial communication. it also has a multiprocessor communication function for serial communication among two or more processors. the sci supports a smart card interface, which is a serial communications feature for ic card interfaces that conforms to the iso/iec standard 7816-3 for identification cards. see section 14, smart card interface, for more information. 14.1.1 features sci features are listed below. ? asynchronous or synchronous can be selected as the serial communication mode. ? asynchronous mode: ? serial data communication is synchronized in start-stop mode in character units. the sci can communicate with a universal asynchronous receiver/transmitter (uart), an asynchronous communication interface adapter (acia), or any other communications chip that employs a standard asynchronous serial system. it can also communicate with two or more other processors using the multiprocessor communication function. the maximum bit rate is 937.5 kbps. there are twelve selectable serial data communication formats. ? data length: seven or eight bits ? stop bit length: one or two bits ? parity: even, odd, or none ? multiprocessor bit: 1 or 0 ? receive error detection: parity, overrun, and framing errors ? break detection: by reading the rxd level directly from the serial port register (scsptr) when a framing error occurs ? synchronous mode: ? serial data communication is synchronized with a clock signal. the sci can communicate with other chips having a synchronous communication function. the maximum bit rate is 5 mbps. there is one serial data communication format. ? data length: eight bits ? receive error detection: overrun errors ? full duplex communication: the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. ? on-chip baud rate generator with selectable bit rates
344 ? internal or external transmit/receive clock source: from either baud rate generator (internal) or sck pin (external) ? four types of interrupts: transmit-data-empty, transmit-end, receive-data-full, and receive- error interrupts are requested independently. ? when the sci is not in use, it can be stopped by halting the clock supplied to it, saving power. 14.1.2 block diagram figure 14.1 shows a block diagram of the sci. rxd txd sck sci scbrr scssr scsptr scscr sctdr sctsr scrdr scrsr scsmr parity generation parity check clock external clock module data bus internal data bus p p?4 p?16 p?64 tei txi rxi eri bus interface baud rate generator transmit/ receive control scrsr: scrdr: sctsr: sctdr: receive shift register receive data register transmit shift register transmit data register scsmr: scscr: scssr: scbrr: scsptr: serial mode register serial control register serial status register bit rate register serial port register figure 14.1 sci block diagram
345 14.1.3 pin configuration the sci has the serial pins summarized in table 14.1. table 14.1 sci pins pin name abbreviation input/output function serial clock pin sck input/output clock input/output receive data pin rxd input receive data input transmit data pin txd output transmit data output note: these pins function as mode input pins md0?d02 after a power-on reset. they are made to function as serial pins by performing sci operation settings with the te, re, ckei, and cke0 bits in scscr and the c/ a bit in scsmr. break status transmission and detection can be performed by means of the sci? scsptr register. 14.1.4 register configuration table 14.2 summarizes the sci internal registers. these registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. table 14.2 registers name abbreviation r/w initial value * 2 address access size serial mode register scsmr r/w h'00 h'fffffe80 8 bit rate register scbrr r/w h'ff h'fffffe82 8 serial control register scscr r/w h'00 h'fffffe84 8 transmit data register sctdr r/w h'ff h'fffffe86 8 serial status register scssr r/(w)* 1 h'84 h'fffffe88 8 receive data register scrdr r h'00 h'fffffe8a 8 serial port register scsptr r/w * 3 h'ffffff7c 8 notes: 1. only 0 can be written, to clear the flags. 2. initialized by a power-on reset and manual reset. 3. initialized to h?0 except bit 2 and 0.bit 2 and 0 are undefined.
346 14.2 register descriptions 14.2.1 receive shift register (scrsr) the receive shift register (scrsr) receives serial data. data input at the rxd pin is loaded into scrsr in the order received, lsb (bit 0) first, converting the data to parallel form. when one byte has been received, it is automatically transferred to scrdr. the cpu cannot read or write scrsr directly. bit: 7 6 5 4 3 2 1 0 bit name: r/w: 14.2.2 receive data register (scrdr) the receive data register (scrdr) stores serial receive data. the sci completes the reception of one byte of serial data by moving the received data from the receive shift register (scrsr) into scrdr for storage. scrsr is then ready to receive the next data. this double buffering allows the sci to receive data continuously. the cpu can read but not write to scrdr. scrdr is initialized to h'00 by a reset and in standby or module standby mode. bit: 7 6 5 4 3 2 1 0 bit name: initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r 14.2.3 transmit shift register (sctsr) the transmit shift register (sctsr) transmits serial data. the sci loads transmit data from the transmit data register (sctdr) into sctsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from sctdr into sctsr and starts transmitting again. if the tdre bit in scssr is 1, however, the sci does not load the sctdr contents into sctsr. the cpu cannot read or write to sctsr directly. bit: 7 6 5 4 3 2 1 0 bit name: r/w:
347 14.2.4 transmit data register (sctdr) the transmit data register (sctdr) is an 8-bit register that stores data for serial transmission. when the sci detects that the transmit shift register (sctsr) is empty, it moves transmit data written in sctdr into sctsr and starts serial transmission. continuous serial transmission is possible by writing the next transmit data in sctdr during serial transmission from sctsr. the cpu can always read and write to sctdr. sctdr is initialized to h'ff by a reset and in standby or module standby mode. bit: 7 6 5 4 3 2 1 0 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 14.2.5 serial mode register (scsmr) the serial mode register (scsmr) is an 8-bit register that specifies the sci serial communication format and selects the clock source for the baud rate generator. the cpu can always read and write to scsmr. scsmr is initialized to h'00 by a reset and in standby or module standby mode. bit: 7 6 5 4 3 2 1 0 bit name: c/ a chr pe o/ e stop mp cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?ommunication mode (c/ a ): selects whether the sci operates in asynchronous or synchronous mode. bit 7: c/ a description 0 asynchronous mode (initial value) 1 synchronous mode
348 bit 6?haracter length (chr): selects 7-bit or 8-bit data in asynchronous mode. in synchronous mode, the data length is always 8 bits, regardless of the chr setting. bit 6: chr description 0 8-bit data (initial value) 1 7-bit data. (when 7-bit data is selected, the msb (bit 7) of the transmit data register is not transmitted.) bit 5?arity enable (pe): selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. in synchronous mode, a parity bit is neither added nor checked, regardless of the pe setting. bit 5: pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked. when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. bit 4?arity mode (o/ e ): selects even or odd parity when parity bits are added and checked. the o/ e setting is used only in asynchronous mode and only when the parity enable bit (pe) is set to 1 to enable parity addition and checking. the o/ e setting is ignored in synchronous mode, and in asynchronous mode when parity addition and checking is disabled. bit 4: o/ e description 0 even parity (initial value) if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 odd parity if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.
349 bit 3?top bit length (stop): selects one or two bits as the stop bit length in asynchronous mode. this setting is used only in asynchronous mode. it is ignored in synchronous mode because no stop bits are added. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. bit 3: stop description 0 one stop bit (initial value) in transmitting, a single 1-bit is added at the end of each transmitted character. 1 two stop bits in transmitting, two 1-bits are added at the end of each transmitted character. bit 2?ultiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, settings of the parity enable (pe) and parity mode (o/ e ) bits are ignored. the mp bit setting is used only in asynchronous mode; it is ignored in synchronous mode. for the multiprocessor communication function, see section 14.3.3, multiprocessor communication. bit 2: mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0?lock select 1 and 0 (cks1 and cks0): these bits select the internal clock source of the on-chip baud rate generator. four clock sources are available: p? p?4, p?16 and p?64. for further information on the clock source, bit rate register settings, and baud rate, see section 14.2.9, bit rate register. bit 1: cks1 bit 0: cks0 description 00p (initial value) 1p /4 10p /16 1p /64 note: p : peripheral clock
350 14.2.6 serial control register (scscr) the serial control register (scscr) operates the sci transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. the cpu can always read and write to scscr. scscr is initialized to h'00 by a reset and in standby or module standby mode. bit: 7 6 5 4 3 2 1 0 bit name: tie rie te re mpie teie cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?ransmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the transmit data register empty bit (tdre) in the serial status register (scssr) is set to 1 due to transfer of serial transmit data from sctdr to sctsr. bit 7: tie description 0 transmit-data-empty interrupt request (txi) is disabled. (initial value) the txi interrupt request can be cleared by reading tdre after it has been set to 1, then clearing tdre to 0, or by clearing tie to 0. 1 transmit-data-empty interrupt request (txi) is enabled. bit 6?eceive interrupt enable (rie): enables or disables the receive-data-full interrupt (rxi) requested when the receive data register full bit (rdrf) in the serial status register (scssr) is set to 1 due to transfer of serial receive data from scrsr to scrdr. it also enables or disables receive-error interrupt (eri) requests. bit 6: rie description 0 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are disabled. (initial value) rxi and eri interrupt requests can be cleared by reading the rdrf flag or error flag (fer, per, or orer) after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. 1 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are enabled. bit 5?ransmit enable (te): enables or disables the sci serial transmitter.
351 bit 5: te description 0 transmitter disabled (initial value) the transmit data register empty bit (tdre) in the serial status register (scssr) is locked at 1. 1 transmitter enabled serial transmission starts when the transmit data register empty (tdre) bit in the serial status register (scssr) is cleared to 0 after writing of transmit data into sctdr. select the transmit format in scsmr before setting te to 1. bit 4?eceive enable (re): enables or disables the sci serial receiver. bit 4: re description 0 receiver disabled (initial value) clearing re to 0 does not affect the receive flags (rdrf, fer, per, orer). these flags retain their previous values. 1 receiver enabled serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. select the receive format in scsmr before setting re to 1. bit 3?ultiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie setting is used only in asynchronous mode, and only if the multiprocessor mode bit (mp) in the serial mode register (scsmr) is set to 1 during reception. the mpie setting is ignored in synchronous mode or when the mp bit is cleared to 0. bit 3: mpie description 0 multiprocessor interrupts are disabled (normal receive operation). (initial value) mpie is cleared to 0 by writing 0 to it, or when the multiprocessor bit (mpb) is set to 1 in receive data. 1 multiprocessor interrupts are enabled. receive-data-full interrupt requests (rxi), receive-error interrupt requests (eri), and setting of the rdrf, fer, and orer status flags in the serial status register (scssr) are disabled until data with a multiprocessor bit of 1 is received. the sci does not transfer receive data from scrsr to scrdr, does not detect receive errors, and does not set the rdrf, fer, and orer flags in the serial status register (scssr). when it receives data that includes mpb = 1, the scssr? mpb flag is set to 1, and the sci automatically clears mpie to 0, generates rxi and eri interrupts (if the tie and rie bits in scscr are set to 1), and allows the fer and orer bits to be set.
352 bit 2?ransmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if sctdr does not contain new transmit data when the msb is transmitted. bit 2: teie description 0 transmit-end interrupt (tei) requests are disabled.* (initial value) 1 transmit-end interrupt (tei) requests are enabled.* note: the tei request can be cleared by reading the tdre bit in the serial status register (scssr) after it has been set to 1, then clearing tdre to 0 and clearing the transmit end (tend) bit to 0, or by clearing the teie bit to 0. bits 1 and 0?lock enable 1 and 0 (cke1 and cke0): these bits select the sci clock source and enable or disable clock output from the sck pin. depending on the combination of cke1 and cke0, the sck pin can be used for serial clock output or serial clock input. the cke0 setting is valid only in asynchronous mode, and only when the sci is internally clocked (cke1 = 0). the cke0 setting is ignored in synchronous mode, or when an external clock source is selected (cke1 = 1). before selecting the sci operating mode in the serial mode register (scsmr), set cke1 and cke0. for further details on selection of the sci clock source, see table 14.9 in section 14.3, operation. bit 1: cke1 bit 0: cke0 description 0 0 asynchronous mode internal clock, sck pin used for input pin (input signal is ignored) (initial value) synchronous mode internal clock, sck pin used for serial clock output (initial value) 1 asynchronous mode internal clock, sck pin used for clock output* 1 synchronous mode internal clock, sck pin used for serial clock output 1 0 asynchronous mode external clock, sck pin used for clock input* 2 synchronous mode external clock, sck pin used for serial clock input 1 asynchronous mode external clock, sck pin used for clock input* 2 synchronous mode external clock, sck pin used for serial clock input notes: 1. the output clock frequency is the same as the bit rate. 2 the input clock frequency is 16 times the bit rate.
353 14.2.7 serial status register (scssr) the serial status register (scssr) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the sci operating status. the cpu can always read and write to scssr, but cannot write 1 in the status flags (tdre, rdrf, orer, per, and fer). these flags can be cleared to 0 only if they have first been read (after being set to 1). bits 2 (tend) and 1 (mpb) are read-only bits that cannot be written. scssr is initialized to h'84 by a reset and in standby or module standby mode. bit: 7 6 5 4 3 2 1 0 bit name: tdre rdrf orer fer per tend mpb mpbt initial value: 1 0 0 0 0 1 0 0 r/w: r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r r r/w note: * only 0 can be written, to clear the flag. bit 7?ransmit data register empty (tdre): indicates that the sci has loaded transmit data from sctdr into sctsr and new serial transmit data can be written in sctdr. bit 7: tdre description 0 sctdr contains valid transmit data. tdre is cleared to 0 when software reads tdre after it has been set to 1, then writes 0 in tdre, or data is written in sctdr. 1 sctdr does not contain valid transmit data. (initial value) tdre is set to 1 when the chip is reset or enters standby mode, the te bit in the serial control register (scscr) is cleared to 0, or sctdr contents are loaded into sctsr, so new data can be written in sctdr.
354 bit 6?eceive data register full (rdrf): indicates that scrdr contains received data. bit 6: rdrf description 0 scrdr does not contain valid received data. (initial value) rdrf is cleared to 0 when the chip is reset or enters standby mode, software reads rdrf after it has been set to 1, then writes 0 in rdrf, or data is read from scrdr. 1 scrdr contains valid received data. rdrf is set to 1 when serial data is received normally and transferred from scrsr to scrdr. note: scrdr and rdrf are not affected by detection of receive errors or by clearing of the re bit to 0 in the serial control register. they retain their previous contents. if rdrf is still set to 1 when reception of the next data ends, an overrun error (orer) occurs and the receive data is lost. bit 5?verrun error (orer): indicates that data reception aborted due to an overrun error. bit 5: orer description 0 receiving is in progress or has ended normally. (initial value) clearing the re bit to 0 in the serial control register does not affect the orer bit, which retains its previous value. orer is cleared to 0 when the chip is reset or enters standby mode or software reads orer after it has been set to 1, then writes 0 in orer. 1 a receive overrun error occurred. scrdr continues to hold the data received before the overrun error, so subsequent receive data is lost. serial receiving cannot continue while orer is set to 1. in synchronous mode, serial transmitting is also disabled. orer is set to 1 if reception of the next serial data ends when rdrf is set to 1.
355 bit 4?raming error (fer): indicates that data reception aborted due to a framing error in asynchronous mode. bit 4: fer description 0 receiving is in progress or has ended normally. (initial value) clearing the re bit to 0 in the serial control register does not affect the fer bit, which retains its previous value. fer is cleared to 0 when the chip is reset or enters standby mode or software reads fer after it has been set to 1, then writes 0 in fer. 1 a receive framing error occurred. when the stop bit length is two bits, only the first bit is checked. the second stop bit is not checked. when a framing error occurs, the sci transfers the receive data into scrdr but does not set rdrf. serial receiving cannot continue while fer is set to 1. in synchronous mode, serial transmitting is also disabled. fer is set to 1 if the stop bit at the end of receive data is checked and found to be 0. bit 3?arity error (per): indicates that data reception (with parity) aborted due to a parity error in asynchronous mode. bit 3: per description 0 receiving is in progress or has ended normally. (initial value) clearing the re bit to 0 in the serial control register does not affect the per bit, which retains its previous value. per is cleared to 0 when the chip is reset or enters standby mode or software reads per after it has been set to 1, then writes 0 in per. 1 a receive parity error occurred. when a parity error occurs, the sci transfers the receive data into scrdr but does not set rdrf. serial receiving cannot continue while per is set to 1. in synchronous mode, serial transmitting is also disabled. per is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (o/e) in the serial mode register (scsmr).
356 bit 2?ransmit end (tend): indicates that when the last bit of a serial character was transmitted, sctdr did not contain valid data, so transmission has ended. tend is a read-only bit and cannot be written. bit 2: tend description 0 transmission is in progress. tend is cleared to 0 when software reads tdre after it has been set to 1, then writes 0 in tdre, or data is written in sctdr. 1 end of transmission. (initial value) tend is set to 1 when the chip is reset or enters standby mode, te is cleared to 0 in the serial control register (scscr), or tdre is 1 when the last bit of a one- byte serial character is transmitted. bit 1?ultiprocessor bit (mpb): stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode. mpb is a read-only bit and cannot be written. bit 1: mpb description 0 multiprocessor bit value in receive data is 0. (initial value) if re is cleared to 0 when a multiprocessor format is selected, the mpb retains its previous value. 1 multiprocessor bit value in receive data is 1. bit 0?ultiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. the mpbt setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the sci is not transmitting. bit 0: mpbt description 0 multiprocessor bit value in transmit data is 0. (initial value) 1 multiprocessor bit value in transmit data is 1.
357 14.2.8 serial port register (scsptr) the serial port register (scsptr) is an 8-bit register that the cpu can always read and write. it controls i/o and data of the port multiplexed with the serial communications interface (sci) pins. input data can be read from the rxd pin and output data can be transmitted to the txd pin; this controls breaks for serial transmission and reception. scsptr is initialized to h'00 by a power-on reset. it is not initialized by a manual reset or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: spb1io spb1dt spb0io spb0dt initial value: 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w bits 7 to 4?eserved: these bits are always read as 0. the write value should always be 0. bit 3?erial port clock port i/o (spb1io): specifies serial port sck pin input/output. when the sck pin is actually set as a port output pin and outputs the value set by the spb1dt bit, the c/ a bit in scsmr and the cke1 and cke0 bits in scscr should be cleared to 0. bit 3: spb1io description 0 the spb1io value is not output to the sck pin. (initial value) 1 the spb1io bit value is output to the txd pin. bit 2?erial port clock port data (spb1dt): specifies the serial port sck pin input/output data. input or output is specified by the spb1io bit (see the description of spb1io for details). when output is specified, the value of the spb1dt bit is output to the sck pin. the sck pin value is read from the spb1dt bit regardless of the value of the spb1io bit. the initial value of this bit after a power-on reset is undefined. bit 2: spb1dt description 0 i/o data level is low. (initial value) 1 i/o data level is high. bit 1?erial port break i/o (spb0io): specifies the serial port txd pin output condition. when the txd pin is actually set as a port output pin and outputs the value set by the spb0dt bit, the te bit in scscr should be cleared to 0.
358 bit 1: spb0io description 0 the spb0dt bit value is not output to the txd pin. (initial value) 1 the spb0dt bit value is output to the txd pin. bit 0?erial port break data (spb0dt): specifies the serial port i/o data. use the spb0io bit to specify input or output of txd pin. spb0dt bit is output to the txd pin when specified as output. the rxd pin value is read from the spb0io bit regardless of the spb0io bit value. the initial value is undefined. bit 0 : spb0dt description 0 i/o data level is low. (initial value) 1 i/o data level is high. block diagrams of the sci i/o port pins are shown in figures 16.2 to 16.4 in section 16, i/o ports. 14.2.9 bit rate register (scbrr) the bit rate register (scbrr) is an 8-bit register that, together with the baud rate generator clock source selected by the cks1 and cks0 bits in the serial mode register (scsmr), determines the serial transmit/receive bit rate. the cpu can always read and write to scbrr. scbrr is initialized to h'ff by a reset and in module standby or standby mode. each channel has independent baud rate generator control, so different values can be set in the two channels. bit: 7 6 5 4 3 2 1 0 bit name: initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the scbrr setting is calculated as follows: asynchronous mode: n = [p /(64 2 2n ?1 b)] 10 6 ?1 synchronous mode: n = [p /(8 2 2n ?1 b)] 10 6 ?1 b: bit rate (bit/s) n: scbrr setting for baud rate generator (0 n 255) p : operating frequency for peripheral modules (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 14.3.)
359 table 14.3 scsmr settings scsmr settings n clock source cks1 cks0 0p 00 1p /4 0 1 2p /16 1 0 3p /64 1 1 note: the bit rate error for asynchronous mode is given by the following formula: error ( % ) = {p( 10 6 )/[(n + 1) b 64 2 2n ?1 ] ?1 } 100 table 14.4 lists examples of scbrr settings in asynchronous mode; table 14.5 lists examples of scbrr settings in synchronous mode. table 14.4 bit rates and scbrr settings in asynchronous mode p (mhz) 2 2.097152 2.4576 bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 141 0.03 1 148 ?.04 1 174 ?.26 150 1 103 0.16 1 108 0.21 1 127 0.00 300 0 207 0.16 0 217 0.21 0 255 0.00 600 0 103 0.16 0 108 0.21 0 127 0.00 1200 0 51 0.16 0 54 ?.70 0 63 0.00 2400 0 25 0.16 0 26 1.14 0 31 0.00 4800 0 12 0.16 0 13 ?.48 0 15 0.00 9600 0 6 ?.99 0 6 ?.48 0 7 0.00 19200 0 2 8.51 0 2 13.78 0 3 0.00 31250 0 1 0.00 0 1 4.86 0 1 22.88 38400 0 1 ?8.62 0 1 ?4.67 0 1 0.00
360 table 14.4 bit rates and scbrr settings in asynchronous mode (cont) p (mhz) 3 3.6864 4 bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 212 0.03 2 64 0.70 2 70 0.03 150 1 155 0.16 1 191 0.00 1 207 0.16 300 1 77 0.16 1 95 0.00 1 103 0.16 600 0 155 0.16 0 191 0.00 0 207 0.16 1200 0 77 0.16 0 95 0.00 0 103 0.16 2400 0 38 0.16 0 47 0.00 0 51 0.16 4800 0 19 ?.34 0 23 0.00 0 25 0.16 9600 0 9 ?.34 0 11 0.00 0 12 0.16 19200 0 4 ?.34 0 5 0.00 0 6 ?.99 31250 0 2 0.00 0 3 0.00 38400 0 2 0.00 0 2 8.51 p (mhz) 4.9152 5 6 bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 86 0.31 2 88 ?.25 2 106 ?.44 150 1 255 0.00 2 64 0.16 2 77 0.16 300 1 127 0.00 1 129 0.16 1 155 0.16 600 0 255 0.00 1 64 0.16 1 77 0.16 1200 0 127 0.00 0 129 0.16 0 155 0.16 2400 0 63 0.00 0 64 0.16 0 77 0.16 4800 0 31 0.00 0 32 ?.36 0 38 0.16 9600 0 15 0.00 0 15 1.73 0 19 ?.34 19200 0 7 0.00 0 7 1.73 0 9 ?.34 31250 0 4 ?.70 0 4 0.00 0 5 0.00 38400 0 3 0.00 0 3 1.73 0 4 ?.34
361 table 14.4 bit rates and scbrr settings in asynchronous mode (cont) p (mhz) 6.144 7.3728 8 bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 108 0.08 2 130 ?.07 2 141 0.03 150 2 79 0.00 2 95 0.00 2 103 0.16 300 1 159 0.00 1 191 0.00 1 207 0.16 600 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 0.00 0 5 0.00 0 6 ?.99 p (mhz) 9.8304 10 12 12.288 bit rate (bit/s) n n error ( % )n n error ( % )n n error ( % )n n error ( % ) 110 2 174 ?.26 2 177 ?.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 0.16 0 19 0.00 31250 0 9 ?.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 1 0.00 0 7 1.73 0 9 ?.34 0 9 0.00
362 table 14.4 bit rates and scbrr settings in asynchronous mode (cont) p (mhz) 14.7456 16 19.6608 20 bit rate (bit/s) n n error ( % )n n error ( % )n n error ( % )n n error ( % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 ?.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 0 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?.36 31250 0 14 ?.70 0 15 0.00 0 19 ?.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 p (mhz) 24 24.576 28.7 30 bit rate (bit/s) n n error ( % )n n error ( % )n n error ( % )n n error ( % ) 110 3 106 ?.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 ?.35 300 2 155 0.16 2 159 0.00 2 186 ?.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 ?.35 1200 1 155 0.16 1 159 0.00 1 186 ?.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 ?.35 4800 0 155 0.16 0 159 0.00 0 186 ?.08 0 194 ?.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 ?.35 19200 0 38 0.16 0 39 0.00 0 46 ?.61 0 48 ?.35 31250 0 23 0.00 0 24 ?.70 0 28 ?.03 0 29 0.00 38400 0 19 ?.34 0 19 0.00 0 22 1.55 0 23 1.73
363 table 14.5 bit rates and scbrr settings in synchronous mode p (mhz) bit rate 4 8 16 28.7 30 (bit/s) n n n n n n n n n n 110 250 2 2493 1243 249 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 09019039071074 250k 0307015029 500k 010307014 1m 0 0* 0 1 0 3 2m 0* 0 0 1 note: settings with an error of 1 % or less are recommended. legend blank: no setting possible ? setting possible, but error occurs *: continuous transmit/receive operation not possible
364 table 14.6 shows the maximum bit rates in asynchronous mode when the baud rate generator is being used. tables 14.7 and 14.8 list the maximum rates for external clock input. table 14.6 maximum bit rates for various frequencies with baud rate generator (asynchronous mode) settings p (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0
365 table 14.7 maximum bit rates during external clock input (asynchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 table 14.8 maximum bit rates during external clock input (synchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bit/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0
366 14.3 operation 14.3.1 overview for serial communication, the sci has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. asynchronous/synchronous mode and the transmission format are selected in the serial mode register (scsmr), as shown in table 14.9. the sci clock source is selected by the combination of the c/ a bit in the serial mode register (scsmr) and the cke1 and cke0 bits in the serial control register (scscr), as shown in table 14.10. asynchronous mode: ? data length is selectable: seven or eight bits. ? parity and multiprocessor bits are selectable, as is the stop bit length (one or two bits). the combination of the preceding selections constitutes the communication format and character length. ? in receiving, it is possible to detect framing errors (fer), parity errors (per), overrun errors (orer) and breaks. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. ? when an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) synchronous mode: ? the transmission/reception format has a fixed eight-bit data length. ? in receiving, it is possible to detect overrun errors (orer). ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and outputs a serial clock to external devices. ? when an external clock is selected, the sci operates on the input serial clock. the on-chip baud rate generator is not used.
367 table 14.9 serial mode register settings and sci communication formats scsmr settings sci communication format mode bit 7 c/ a bit 6 chr bit 5 pe bit 2 mp bit 3 stop data length parity bit multipro- cessor bit stop bit length asynchronous 0 0000 8-bit not used not used 1 bit 1 2 bits 1 0 used 1 bit 1 2 bits 1 0 0 7-bit not used 1 bit 1 2 bits 1 0 used 1 bit 1 2 bits asynchronous 0 * 1 0 8-bit not used used 1 bit (multiprocessor * 1 2 bits format) 1 * 0 7-bit 1 bit * 1 2 bits synchronous 1 **** 8-bit not used none note: asterisks (*) indicate don?-care bits. table 14.10 scsmr and scscr settings and sci clock source selection scsmr scscr settings sci transmit/receive clock mode bit 7 c/ a bit 1 cke1 bit 0 cke0 clock source sck pin function asynchronous 0 0 0 internal sci does not use the sck pin mode 1 outputs a clock with frequency matching the bit rate 1 0 external inputs a clock with frequency 16 1 times the bit rate synchronous 1 0 0 internal outputs the serial clock mode 1 1 0 external inputs the serial clock 1
368 14.3.2 operation in asynchronous mode in asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci are independent, so full-duplex communication is possible. the transmitter and receiver are both double-buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 14.2 shows the general format of asynchronous serial communication. in asynchronous serial communication, the communication line is normally held in the mark (high) state. the sci monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and stop bit (high), in that order. when receiving in asynchronous mode, the sci synchronizes on the falling edge of the start bit. the sci samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. 0d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 1 0/1 1 1 (lsb) (msb) serial data start bit 1 bit transmit/receive data 7 or 8 bits one unit of communication data (character or frame) idle (mark) state parity bit stop bit 1 or no bit 1 or 2 bits figure 14.2 data format in asynchronous communication (example: 8-bit data with parity and 2 stop bits) transmit/receive formats: table 14.11 lists the 12 communication formats that can be selected in asynchronous mode. the format is selected by settings in the serial mode register (scsmr).
369 table 14.11 serial communication formats (asynchronous mode) scsmr bits serial transmit/receive format and frame length chr pe mp stop 1 2345678 9 10 11 12 0 0 0 0 s 8-bit data stop 0 0 0 1 s 8-bit data stop stop 0 1 0 0 s 8-bit data p stop 0 1 0 1 s 8-bit data p stop stop 1 0 0 0 s 7-bit data stop 1 0 0 1 s 7-bit data stop stop 1 1 0 0 s 7-bit data p stop 1 1 0 1 s 7-bit data p stop stop 0 1 0 s 8-bit data mpb stop 0 1 1 s 8-bit data mpb stop stop 1 1 0 s 7-bit data mpb stop 1 1 1 s 7-bit data mpb stop stop legend : don t care bits s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci transmit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (scsmr) and bits cke1 and cke0 in the serial control register (scscr) (table 14.10). when an external clock is input at the sck pin, it must have a frequency equal to 16 times the desired bit rate. when the sci operates on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to the bit rate. the phase is aligned as shown in figure 14.3 so that the rising edge of the clock occurs at the center of each transmit data bit.
370 0 d0d1d2d3d4d5d6d70/1 1 1 1 frame figure 14.3 output clock and serial data timing (asynchronous mode) transmitting and receiving data (sci initialization (asynchronous mode)): before transmitting or receiving, clear the te and re bits to 0 in the serial control register (scscr), then initialize the sci as follows. when changing the operation mode or communication format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (sctsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags or receive data register (scrdr), which retain their previous contents. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. sci operation becomes unreliable if the clock is stopped. figure 14.4 is a sample flowchart for initializing the sci. the procedure for initializing the sci is: 1. select the clock source in the serial control register (scscr). leave rie, tie, teie, mpie, te, and re cleared to 0. if clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in scscr. 2. select the communication format in the serial mode register (scsmr). 3. write the value corresponding to the bit rate in the bit rate register (scbrr) unless an external clock is used. 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scscr) to 1. also set rie, tie, teie, and mpie as necessary. setting te or re enables the sci to use the txd or rxd pin. the initial states are the mark transmit state, and the idle receive state (waiting for a start bit).
371 initialize clear te and re bits in scscr to 0 select transmit/receive format in scsmr set value to scbrr set cke1 and cke0 bits in scscr (te and re bits are 0) wait set te and re bits in scscr to 1 and set rie, teie, and mpie bits has a 1-bit interval elapsed? end (2) (3) (1) (4) no yes note: numbers in parentheses refer to the preceding procedure. figure 14.4 sample flowchart for sci initialization transmitting serial data (asynchronous mode): figure 14.5 shows a sample flowchart for transmitting serial data. the procedure for transmitting serial data is: 1. sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr) and clear tdre to 0. 2. to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0. 3. to output a break at the end of serial transmission: clear the spb0dt bit in the scsptr, set the spb0io bit to 1 and then clear the te bit to 0 in scscr.
372 start transmission read tdre bit in scssr read tend bit in scssr clear te bit in scscr to 0 tend = 1? end transmission (1) (2) (3) no yes tdre = 1? write transmit data to tdr and clear tdre bit in scssr to 0 all data transmitted? no yes break output? no yes clear spb0dt to 0 and set spb0io to 1 yes no note: numbers in parentheses refer to the preceding procedure. figure 14.5 sample flowchart for transmitting serial data
373 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in scssr. when tdre is cleared to 0, the sci recognizes that the transmit data register (sctdr) contains new data, and loads this data from sctdr into the transmit shift register (sctsr). 2. after loading the data from sctdr into sctsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) is set to 1 in scscr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits of data are output, lsb first. c. parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads new data from sctdr into sctsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit to 1 in scssr, outputs the stop bit, then continues output of 1 bits (marking). if the transmit-end interrupt enable bit (teie) in scscr is set to 1, a transmit-end interrupt (tei) is requested.
374 figure 14.6 shows an example of sci transmit operation in asynchronous mode. 01 1 1 0/1 0 1 tdre tend parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (mark) state txi interrupt request tei interrupt request txi interrupt handler writes data to tdr and clears tdre bit to 0 1 frame d 0 d 1 d 7 d 0 d 1 d 7 0/1 txi interrupt request figure 14.6 sci transmit operation in asynchronous mode (example: 8-bit data with parity and one stop bit) receiving serial data (asynchronous mode): figure 14.7 and 14.8 shows a sample flowchart for receiving serial data. the procedure for receiving serial data after enabling the sci for reception is: 1. receive error handling and break detection: if a receive error occurs, read the orer, per and fer bits in scssr to identify the error. after executing the necessary error handling, clear orer, per and fer all to 0. receiving cannot resume if orer, per or fer remain set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. 2. sci status check and receive-data read: read the serial status register (scssr), check that rdrf is set to 1, then read receive data from the receive data register (scrdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 3. to continue receiving serial data: read the rdrf and scrdr bits and clear rdrf to 0 before the stop bit of the current frame is received.
375 start reception read orer, per, and fer bits in scssr all data received? end reception (1) no yes per, fer, orer = 1? rdrf = 1? yes yes clear the re bit in scscr to 0 no no read the rdrf bit in scssr error handling (3) (2) read reception data of scrdr and clear rdrf bit in scssr to 0 note: numbers in parentheses refer to the preceding procedure. figure 14.7 sample flowchart for receiving serial data
376 error handling orer = 1? overrun error handling fer = 1? yes break? no framing error handling per = 1? yes parity error handling clear orer, per, and fer bits in scssr to 0 end no no no yes yes clear re bit in scscr to 0 figure 14.8 sample flowchart for receiving serial data (cont)
377 in receiving, the sci operates as follows: 1. the sci monitors the communication line. when it detects a start bit (0), the sci synchronizes internally and starts receiving. 2. receive data is shifted into scrsr in order from the lsb to the msb. 3. the parity bit and stop bit are received. after receiving these bits, the sci makes the following checks: a. parity check: the number of 1s in the receive data must match the even or odd parity setting of the o/ e bit in scsmr. b. stop bit check: the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. c. status check: rdrf must be 0 so that receive data can be loaded from scrsr into scrdr. if these checks all pass, the sci sets rdrf to 1 and stores the received data in scrdr. if one of the checks fails (receive error), the sci operates as indicated in table 14.12. note: when a receive error flag is set, further receiving is disabled. the rdrf bit is not set to 1. be sure to clear the error flags. 4. after setting rdrf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in scscr, the sci requests a receive-data-full interrupt (rxi). if one of the error flags (orer, per, or fer) is set to 1 and the receive-data-full interrupt enable bit (rie) in scscr is also set to 1, the sci requests a receive-error interrupt (eri). table 14.12 receive error conditions and sci operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf is still set to 1 in scssr receive data not loaded from scrsr into scrdr framing error fer stop bit is 0 receive data loaded from scrsr into scrdr parity error per parity of receive data differs from even/odd parity setting in scsmr receive data loaded from scrsr into scrdr figure 14.9 shows an example of sci receive operation in asynchronous mode.
378 rdrf fer eri interrupt request generated by framing error 1 frame rxi interrupt handler reads data and clears rdrf bit to 0 rxi interrupt request 01 1 1 0/1 0 1 parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (mark) state d 0 d 1 d 7 d 0 d 1 d 7 0/1 figure 14.9 sci receive operation (example: 8-bit data with parity and one stop bit) 14.3.3 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by a unique id. a serial communication cycle consists of an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their ids. the receiving processor with a matching id continues to receive further incoming data. processors with ids not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way.
379 figure 14.10 shows an example of communication among processors using the multiprocessor format. receiving station a (id = 01) (id = 02) (id = 03) (id = 04) receiving station b receiving station c serial communication circuit h'01 h'aa (mpb = 0) (mpb = 1) id transmit cycle = specifies receiving station serial data transmitting station receiving station d data transmit cycle = data transmission to receiving station specified by id mpb: multiprocessor bit figure 14.10 communication among processors using multiprocessor format (example: sending data h'aa to receiving processor a) communication formats: four formats are available. parity-bit settings are ignored when the multiprocessor format is selected. for details see table 14.11. clock: see the description in the asynchronous mode section. transmitting multiprocessor serial data: figure 14.11 shows a sample flowchart for transmitting multiprocessor serial data. the procedure for transmitting multiprocessor serial data is: 1. sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr). also set mpbt (multiprocessor bit transfer) to 0 or 1 in scssr. finally, clear tdre to 0. 2. to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0. 3. to output a break at the end of serial transmission: set the spb0dt bit in the scsptr register to 0, set spb0io to 1, then clear te to 0 in scscr.
380 tdre = 1? write transmission data to tdr and set mpbt bit in scssr transmission ended? yes tend = 1? read tend bit in scssr break output? yes clear spb0dt to 0, set spb0io to 1 clear te bit scscr to 0 end transmission yes read tdre bit in scssr clear tdre bit to 0 no no yes no no (1) (2) (3) start transmission note: numbers in parentheses refer to the preceding procedure. figure 14.11 sample flowchart for transmitting multiprocessor serial data
381 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in scssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (sctdr) contains new data, and loads this data from sctdr into the transmit shift register (sctsr). 2. after loading the data from sctdr into sctsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in the scscr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits are output, lsb first. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads data from sctdr into sctsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in scssr to 1, outputs the stop bit, then continues output of 1 bits in the mark state. if the transmit-end interrupt enable bit (teie) in the scscr is set to 1, a transmit-end interrupt (tei) is requested at this time.
382 figure 14.12 shows sci transmission with the multiprocessor format. tdre tend txi interrupt request txi interrupt request tei interrupt request txi interrupt handler writes data to tdr and clears tdre bit to 0 1 frame 01 1 1 0/1 0 1 multi- processor bit serial data start bit data stop bit start bit data stop bit idle (mark) state d 0 d 1 d 7 d 0 d 1 d 7 0/1 multi- processor bit figure 14.12 sci multiprocessor transmit operation (example: 8-bit data with multiprocessor bit and one stop bit) receiving multiprocessor serial data: figure 14.13 shows a sample flowchart for receiving multiprocessor serial data. the procedure for receiving multiprocessor serial data is: 1. id receive cycle: set the mpie bit in the serial control register (scscr) to 1. 2. sci status check and compare to id reception: read the serial status register (scssr), check that rdrf is set to 1, then read data from the receive data register (scrdr) and compare with the processor? own id. if the id does not match the receive data, set mpie to 1 again and clear rdrf to 0. if the id matches the receive data, clear rdrf to 0. 3. sci status check and data receiving: read scssr, check that rdrf is set to 1, then read data from the receive data register (scrdr). 4. receive error handling and break detection: if a receive error occurs, read the orer and fer bits in scssr to identify the error. after executing the necessary error handling, clear both orer and fer to 0. receiving cannot resume if orer or fer remain set to 1. when a framing error occurs, the rxd pin can be read to detect the break state.
383 rdrf = 1? fer = 1 or orer = 1? rdrf = 1? all data received? no end reception yes set mpie bit in scscr to 1 read rdrf bit in scssr clear re bit in scscr to 0 no no (1) (2) read orer and fer bits in scssr fer = 1 or orer = 1? read rdrf bit in scssr read receive data in scrdr is id the station s id? yes read orer and fer bits in sscsr (4) no error handling yes yes (3) yes no start reception no yes read receive data in scrdr note: numbers in parentheses refer to the preceding procedure. figure 14.13 sample flowchart for receiving multiprocessor serial data
384 orer = 1? break? yes framing error handling yes error handling overrun error handling yes fer = 1? clear orer and fer bits in scssr to 0 end no no no clear re bit in scscr to 0 figure 14.14 sample flowchart for receiving multiprocessor serial data (cont)
385 figures 14.15 and 14.16 show examples of sci receive operation using a multiprocessor format. rdrf mpie rdr value id1 rxi interrupt request (multiprocessor interrupt), mpie = 0 rxi interrupt handler reads rdr data and clears rdrf bit to 0 id is not station s id, so mpie bit is set to 1 again no rxi interrupt, rdr state is maintained 01 1 1 10 1 stop bit mpb serial data start bit data (id1) data (data 1) start bit mpb stop bit idle (mark) state d 0 d 1 d 7 d 0 d 1 d 7 0 figure 14.15 example of sci receive operation: own id does not match data (8-bit data with multiprocessor bit and one stop bit)
386 rdrf mpie rdr value id1 id2 data2 01 1 1 10 1 mpb mpb serial data start bit data (id2) data (data 2) stop bit start bit stop bit idle (mark) state d 0 d 1 d 7 d 0 d 1 d 7 0 rxi interrupt request (multiprocessor interrupt), mpie = 0 rxi interrupt handler reads rdr data and clears rdrf bit to 0 id is that of station, so reception continues unchanged and data is received by the rxi interrupt handler mpie bit set to 1 again figure 14.16 example of sci receive operation: own id matches data (8-bit data with multiprocessor bit and one stop bit) 14.3.4 synchronous operation in synchronous mode, the sci transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. the transmitter and receiver are also double-buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 14.17 shows the general format in synchronous serial communication.
387 bit 0 care don t care don t bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb msb serial clock serial data ** one unit of communication data (character or frame) note: high except in continuous transmitting or receiving figure 14.17 data format in synchronous communication in synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. data is guaranteed valid at the rising edge of the serial clock. in each character, the serial data bits are transmitted in order from the lsb (first) to the msb (last). after output of the msb, the communication line remains in the state of the msb. in synchronous mode, the sci transmits or receives data by synchronizing with the falling edge of the serial clock. communication format: the data length is fixed at eight bits. no parity bit or multiprocessor bit can be added. clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci transmit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (scsmr) and bits cke1 and cke0 in the serial control register (scscr). see table 14.10. when the sci operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received character. when the sci is not transmitting or receiving, the clock signal remains in the high state. when only receiving, the sci receives in 2- character units, so a 16 pulse synchronization clock is output. to receive in 1-character units, select an external clock source. transmitting and receiving data: sci initialization (synchronous mode). before transmitting, receiving, or changing the mode or communication format, the software must clear the te and re bits to 0 in the serial control register (scscr), then initialize the sci. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (sctsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (scrdr), which retain their previous contents.
388 figure 14.18 is a sample flowchart for initializing the sci. the procedure for initializing the sci is: 1. select the clock source in the serial control register (scscr). leave rie, tie, teie, mpie, te and re cleared to 0. 2. select the communication format in the serial mode register (scsmr). 3. write the value corresponding to the bit rate in the bit rate register (scbrr) unless an external clock is used. 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scscr) to 1. also set rie, tie, teie and mpie. setting te and re allows use of the txd and rxd pins. initialize clear te and re bits in scscr to 0 (1) has a 1-bit period elapsed? set te and re bits in scscr to 1 and set rie, tie, teie, and mpie bits set transmit/receive format in scsmr yes no set value in scbrr set rie, tie, teie, mpie, cke1, and cke0 bits in scscr (te and re are 0) end wait (2) (3) (4) note: numbers in parentheses refer to the preceding procedure. figure 14.18 sample flowchart for sci initialization
389 transmitting serial data (synchronous mode): figure 14.19 shows a sample flowchart for transmitting serial data. the procedure for transmitting serial data is: 1. sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr) and clear tdre to 0. 2. to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0. start transmission read tdre bit in scssr all data transmitted? yes no end transmission (1) (2) tdre = 1? write transmit data to sctdr and clear tdre bit in scssr to 0 yes no read tend bit in scssr tend = 1? yes no clear te bit in scscr to 0 note: numbers in parentheses refer to the preceding procedure. figure 14.19 sample flowchart for serial transmitting
390 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in scssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (sctdr) contains new data and loads this data from sctdr into the transmit shift register (sctsr). 2. after loading the data from sctdr into sctsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in scscr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. if clock output mode is selected, the sci outputs eight synchronous clock pulses. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data is output from the txd pin in order from the lsb (bit 0) to the msb (bit 7). 3. the sci checks the tdre bit when it outputs the msb (bit 7). if tdre is 0, the sci loads data from sctdr into sctsr, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in scssr to 1, transmits the msb, then holds the transmit data pin (txd) in the msb state. if the transmit-end interrupt enable bit (teie) in the scscr is set to 1, a transmit-end interrupt (tei) is requested at this time. 4. after the end of serial transmission, the sck pin is held in the high state. figure 14.20 shows an example of sci transmit operation. bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 serial clock serial data transfer direction bit 7 txi interrupt handler writes data to tdr and clears tdre bit to 0 1 frame tdre tend lsb msb txi interrupt request txi interrupt request tei interrupt request figure 14.20 example of sci transmit operation
391 receiving serial data (synchronous mode): figure 14.21 shows a sample flowchart for receiving serial data. when switching from asynchronous mode to synchronous mode, make sure that orer, per, and fer are cleared to 0. if per or fer is set to 1, the rdrf bit will not be set and both transmitting and receiving will be disabled. the procedure for receiving serial data is: 1. receive error handling and break detection: if a receive error occurs, read the orer bit in scssr to identify the error. after executing the necessary error handling, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. 2. sci status check and receive data read: read the serial status register (scssr), check that rdrf is set to 1, then read receive data from the receive data register (scrdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 3. to continue receiving serial data: read scrdr, and clear rdrf to 0 before the msb (bit 7) of the current frame is received.
392 read orer bit in scssr all data received? end reception no yes orer = 1? rdrf = 1? yes clear re bit in scscr to 0 no no read rdrf bit in scssr (3) (2) yes error handling (1) read receive data in scrdr and clear rdrf bit in scssr to 0 start reception end orer = 1? no clear orer bit in scssr to 0 yes overrun error handling note: numbers in parentheses refer to the preceding procedure. figure 14.21 sample flowchart for serial receiving in receiving, the sci operates as follows: 1. the sci synchronizes with serial clock input or output and initializes internally. 2. receive data is shifted into scrsr in order from the lsb to the msb. after receiving the data, the sci checks that rdrf is 0 so that receive data can be loaded from scrsr into scrdr. if this check is passed, the sci sets rdrf to 1 and stores the received data in scrdr. if the check is not passed (receive error), the sci operates as indicated in table 14.12. this state prevents further transmission or reception. while receiving, the rdrf bit is not set to 1. be sure to clear the error flag. 3. after setting rdrf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in scscr, the sci requests a receive-data-full interrupt (rxi). if the orer bit is set to 1 and the receive- data-full interrupt enable bit (rie) in scscr is also set to 1, the sci requests a receive-error interrupt (eri).
393 figure 14.22 shows an example of the sci receive operation. bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 serial clock serial data transfer direction bit 7 rxi interrupt handler reads data and clears rdrf bit to 0 1 frame rxi interrupt request rxi interrupt request eri interrupt request generated by overrun error rdrf orer figure 14.22 example of sci receive operation transmitting and receiving serial data simultaneously (synchronous mode): figure 14.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. the procedure for setting the sci to transmit and receive serial data simultaneously is: 1. sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr) and clear tdre to 0. the txi interrupt can also be used to determine if the tdre bit has changed from 0 to 1. 2. receive error handling: if a receive error occurs, read the orer bit in scssr to identify the error. after executing the necessary error handling, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. 3. sci status check and receive data read: read the serial status register (scssr), check that rdrf is set to 1, then read receive data from the receive data register (scrdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 4. to continue transmitting and receiving serial data: read the rdrf bit and scrdr, and clear rdrf to 0 before the msb (bit 7) of the current frame is received. also read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0 before the msb (bit 7) of the current frame is transmitted.
394 start transmission/reception read tdre bit in scssr all data transmitted/received? end transmission/reception (1) no yes tdre = 1? write transmission data to sctdr and clear tdre bit in scssr to 0 rdrf = 1? no yes yes no read orer bit in scssr error handling (2) orer = 1? no read rdrf bit in scssr (4) yes (3) read receive data of scrdr and clear rdrf bit in scssr to 0 clear te and re bits in scscr to 0 notes: 1. when switching from transmitting or receiving to simultaneous transmitting and receiving, simultaneously clear te and re to 0, then simultaneously set te and re to 1. 2. numbers in parentheses refer to the preceding procedure. figure 14.23 sample flowchart for serial transmitting
395 14.4 sci interrupt sources the sci has four interrupt sources in each channel: transmit-end (tei), receive-error (eri), receive-data-full (rxi), and transmit-data-empty (txi). table 14.13 lists the interrupt sources and indicates their priority. these interrupts can be enabled and disabled by the tie, rie, and teie bits in the serial control register (scscr). each interrupt request is sent separately to the interrupt controller. txi is requested when the tdre bit in scssr is set to 1. tdre is automatically cleared to 0 when data is written in the transmit data register (sctdr). rxi is requested when the rdrf bit in scssr is set to 1. rdrf is automatically cleared to 0 when the receive data register (scrdr) is read. eri is requested when the orer, per, or fer bit in scssr is set to 1. tei is requested when the tend bit in scssr is set to 1. where the txi interrupt indicates that transmit data writing is enabled, the tei interrupt indicates that the transmit operation is complete. table 14.13 sci interrupt sources interrupt source description priority when reset is cleared eri receive error (orer, per, or fer) high rxi receive data full (rdrf) txi transmit data empty (tdre) see section 4, exception handling, for information on the priority order and relationship to non- sci interrupts. 14.5 usage notes note the following points when using the sci. sctdr write and tdre flags: the tdre bit in the serial status register (scssr) is a status flag indicating loading of transmit data from sctdr into sctsr. the sci sets tdre to 1 when it transfers data from sctdr to sctsr. data can be written to sctdr regardless of the tdre bit status. if new data is written in sctdr when tdre is 0, however, the old data stored in sctdr will be lost because the data has not yet been transferred to sctsr. before writing transmit data to sctdr, be sure to check that tdre is set to 1.
396 simultaneous multiple receive errors: table 14.14 shows the state of the scssr status flags when multiple receive errors occur simultaneously. when an overrun error occurs, the scrsr contents cannot be transferred to scrdr, so receive data is lost. table 14.14 scssr status flags and transfer of receive data scssr status flags receive data transfer receive error status rdrf orer fer per scrsr scrdr overrun error 1 1 0 0 x framing error 0 0 1 0 o parity error 0 0 0 1 o overrun error + framing error 1 1 1 0 x overrun error + parity error 1 1 0 1 x framing error + parity error 0 0 1 1 o overrun error + framing error + parity error 1 1 1 1 x o: receive data is transferred from scrsr to scrdr. x: receive data is not transferred from scrsr to scrdr. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state, the input from the rxd pin consists of all 0s, so fer is set and the parity error flag (per) may also be set. in the break state, the sci receiver continues to operate, so if the fer bit is cleared to 0, it will be set to 1 again. sending a break signal: the input/output direction and level of the txd pin can be set using the spb0io and spb0dt bits in the serial port register (scsptr). use these bits to send breaks. after initialization, the pin will not function as a txd pin until the te bit is set to 1 (enabling transmission). through this period, the value of the spb0dt bit substitutes for the mark state. for this reason, the spb0io and spb0dt bits are initially set to 1 (output, high level). to send a break during serial transmission, clear the spb0dt bit to 0 (low level), then clear te to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized without regard to the current transmission status, and 0 is output from the txd pin. receive error flags and transmitter operation (synchronous mode only): when a receive error flag (orer, per, or fer) is set to 1, the sci will not start transmitting even if tdre is set to 1. be sure to clear the receive error flags to 0 before starting to transmit. note that clearing re to 0 does not clear the receive error flags. receive data sampling timing and receive margin in asynchronous mode: in asynchronous mode, the sci operates on a base clock of 16 times the transfer rate frequency. in receiving, the sci synchronizes internally with the falling edge of the start bit, which it samples on the base clock. receive data is latched on the rising edge of the eighth base clock pulse (figure 14.24).
397 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 base clock receive data (rxd) synchro- nization sampling timing data sampling timing 8 clock cycles 16 clock cycles start bit 7.5 clock cycles +7.5 clock cycles d0 d1 figure 14.24 receive data sampling timing in asynchronous mode the receive margin in the asynchronous mode can therefore be expressed as shown in equation 1. equation 1: m = 0.5 1 2n d 0.5 n (l 0.5)f (1 + f) where: m = receive margin ( % ) n = ratio of clock frequency to bit rate (n = 16) d = clock duty cycle (d = 0?.0) l = frame length (l = 9?2) f = absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875%, as shown in equation 2. equation 2: m = 1/(2 % = % this is a theoretical value. a reasonable margin to allow in system designs is 20?0%.
398 cautions on use of clock synchronous external clock mode: ? set te = re = 1 only when the external clock sck is 1. ? do not set te = re = 1 until at least four peripheral operating clock cycles after the external clock sck has changed from 0 to 1. ? when receiving, rdrf is 1 when re is set to zero 2.5?.5 peripheral operating clock cycles after the rising edge of the rxd d7 bit sck input, but it cannot be copied to scrdr. caution on use of clock synchronous internal clock mode: when receiving, rdrf is 1 when re is set to zero 1.5 peripheral operating clock cycles after the rising edge of the rxd d7 bit sck output, but it cannot be copied to scrdr.
399 section 15 smart card interface 15.1 overview as an added serial communications interface function, the sci supports an ic card (smart card) interface that conforms to the iso/iec standard 7816-3 for identification of cards. register settings are used to switch between the ordinary serial communication interface and the smart card interface. 15.1.1 features the smart card interface has the following features: ? asynchronous mode ? data length: eight bits ? parity bit generation and check ? receive mode error signal detection (parity error) ? transmit mode error signal detection and automatic re-transmission of data ? supports both direct convention and inverse convention ? bit rate can be selected using on-chip baud rate generator. ? three types of interrupts: transmit-data-empty, receive-data-full, and communication-error interrupts are requested independently.
400 15.1.2 block diagram figure 15.1 shows a block diagram of the smart card interface. rxd txd sck sci scbrr scscr scsmr sctdr sctsr scrdr scrsr scsptr scscmr scssr parity generation parity check clock external clock module data bus internal data bus p p?4 p?16 p?64 txi rxi eri bus interface baud rate generator transmit/ receive control scscmr: scrsr: scrdr: sctsr: sctdr: scsmr: scscr: scssr: scbrr: scsptr: smart card mode register receive data register receive data register transmit shift register transmit data register serial mode register serial control register serial status register bit rate register serial port register figure 15.1 smart card interface block diagram
401 15.1.3 pin configuration table 15.1 summarizes the smart card interface pins. table 15.1 sci pins pin name abbreviation input/output function serial clock pin sck output clock output receive data pin rxd input receive data input transmit data pin txd output transmit data output 15.1.4 register configuration table 15.2 summarizes the registers used by the smart card interface. the scsmr, scbrr, scscr, sctdr, and scrdr registers are the same as in the ordinary sci function. they are described in section 13, serial communication interface. table 15.2 registers name abbreviation r/w initial value* 3 address access size serial mode register scsmr r/w h'00 h'fffffe80 8 bit rate register scbrr r/w h'ff h'fffffe82 8 serial control register scscr r/w h'00 h'fffffe84 8 transmit data register sctdr r/w h'ff h'fffffe86 8 serial status register scssr r/(w)* 1 h'84 h'fffffe88 8 receive data register scrdr r h'00 h'fffffe8a 8 smart card mode register scscmr r/w * 2 h'fffffe8c 8 notes: 1. only 0 can be written, to clear the flags. 2. bits 0, 2, and 3 are cleared. the value of the other bits is undefined. 3. initialized by a power-on or manual reset. 15.2 register descriptions this section describes the registers added for the smart card interface and the bits whose functions are changed.
402 15.2.1 smart card mode register (scscmr) the smart card mode register (scscmr) is an 8-bit read/write register that selects smart card interface functions. scsmr bits 0, 2, and 3 are initialized to 0 by a reset and in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: sdir sinv smif initial value: * * * * 0 0 * 0 r/w: r r r r r/w r/w r r/w note: * undefined bits 7 to 4 and 1?eserved: an undefined value will be returned if these bits are read. bit 3?mart card data transfer direction (sdir): selects the serial/parallel conversion format. bit 3: sdir description 0 contents of sctdr are transferred lsb first, receive data is stored in scrdr lsb first. (initial value) 1 contents of sctdr are transferred msb first, receive data is stored in scrdr msb first. bit 2?mart card data inversion (sinv): specifies whether to invert the logic level of the data. this function is used in combination with bit 3 for transmitting and receiving with an inverse convention card. sinv does not affect the logic level of the parity bit. see section 15.3.4, register settings, for information on how parity is set. bit 2: sinv description 0 contents of sctdr are transferred unchanged, receive data is stored in scrdr unchanged. (initial value) 1 contents of sctdr are inverted before transfer, receive data is inverted before storage in scrdr. bit 0?mart card interface mode select (smif): enables the smart card interface function. bit 0 : smif description 0 smart card interface function disabled (initial value) 1 smart card interface function enabled
403 15.2.2 serial status register (scssr) in the smart card interface mode, the function of scssr bit 4 is changed. the setting conditions for bit 2, the tend bit, are also changed. bit: 7 6 5 4 3 2 1 0 bit name: tdre rdrf orer fer/ers per tend mpb mpbt initial value: 1 0 0 0 0 1 0 0 r/w: r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r r r/w note: * only 0 can be written, to clear the flag. bits 7 to 5: these bits have the same function as in the ordinary sci. see section 13, serial communication interface, for more information. bit 4?rror signal status (ers): in the smart card interface mode, bit 4 indicates the status of the error signal returned from the receiving side during transmission. the smart card interface cannot detect framing errors. bit 4: ers description 0 receiving ended normally with no error signal. (initial value) ers is cleared to 0 when the chip is reset or enters standby mode, or when software reads ers after it has been set to 1, then writes 0 in ers. 1 an error signal indicating a parity error was transmitted from the receiving side. ers is set to 1 if the error signal sampled is low. note: the ers flag maintains its status even when the te bit in scscr is cleared to 0.
404 bits 3 to 0: these bits have the same function as in the ordinary sci. see section 13, serial communication interface, for more information. the setting conditions for bit 2, the transmit end bit (tend), are changed as follows. bit 2: tend description 0 transmission is in progress. tend is cleared to 0 when software reads tdre after it has been set to 1, then writes 0 in tdre, or when data is written in sctdr. 1 end of transmission. (initial value) tend is set to 1 when: ? the chip is reset or enters standby mode, ? the te bit in scscr is 0 and the fer/ers bit is also 0, ? the c/ a bit in scsmr is 0, and tdre = 1 and fer/ers = 0 (normal transmission) 2.5 etu after a one-byte serial character is transmitted, or ? the c/ a bit in scsmr is 1, and tdre = 1 and fer/ers = 0 (normal transmission) 1.0 etu after a one-byte serial character is transmitted. note: etu is an abbreviation of elementary time unit, which is the period for the transfer of 1 bit. 15.3 operation 15.3.1 overview the primary functions of the smart card interface are described below. 1. each frame consists of 8 data bits and 1 parity bit. 2. during transmission, the card leaves a guard time of at least 2 etu (elementary time units: the period for 1 bit to transfer) from the end of the parity bit to the start of the next frame. 2. during reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed from the start bit if a parity error was detected. 4. during transmission, it automatically transmits the same data after allowing at least 2 etu from the time the error signal is sampled. 5. only start-stop type asynchronous communication functions are supported; no synchronous communication functions are available.
405 15.3.2 pin connections figure 15.2 shows the pin connection diagram for the smart card interface. during communication with an ic card, transmission and reception are both carried out over the same data transfer line, so connect the txd and rxd pins on the chip. pull up the data transfer line to the power supply v cc side with a resistor. when using the clock generated by the smart card interface on an ic card, input the sck pin output to the ic card? clk pin. this connection is not necessary when the internal clock is used on the ic card. use the chip? port output as the reset signal. apart from these pins, the power and ground pin connections are usually also required. note: when the ic card is not connected and both re and te are set to 1, closed communication is possible and auto-diagnosis can be performed. lsi txd io clk rst rxd sck px (port) clock line data line reset line ic card connected device v cc figure 15.2 pin connection diagram for the smart card interface
406 15.3.3 data format figure 15.3 shows the data format for the smart card interface. in this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. during transmission, error signals are sampled and data re-transmitted whenever an error signal is detected. ds d0 d1 d2 d3 d4 d5 d6 d7 dp with no parity error transmitting station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp de with parity error transmitting station output receiving station output ds: d0 d7: dp: de: start bit data bits parity bit error signal figure 15.3 data format for smart card interface
407 the operating sequence is: 1. the data line is high impedance when not in use and is fixed high with a pull-up resistor. 2. the transmitting side starts one frame of data transmission. the data frame starts with a start bit (ds, low level). the start bit is followed by eight data bits (d0?7) and a parity bit (dp). 3. on the smart card interface, the data line returns to high impedance after this. the data line is pulled high with a pull-up resistor. 4. the receiving side checks parity. when the data is received normally with no parity errors, the receiving side then waits to receive the next data. when a parity error occurs, the receiving side outputs an error signal (de, low level) and requests re-transfer of data. the receiving station returns the signal line to high impedance after outputting the error signal for a specified period. the signal line is pulled high with a pull-up resistor. 5. the transmitting side transmits the next frame of data unless it receives an error signal. if it does receive an error signal, it returns to step 2 to re-transmit the erroneous data. 15.3.4 register settings table 15.3 shows the bit map of the registers that the smart card interface uses. bits shown as 1 or 0 must be set to the indicated value. the settings for the other bits are described below. table 15.3 register settings for the smart card interface register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scsmr h'fffffe80 c/ a e sdir sinv smif note: dashes indicate unused bits.
408 1. setting the serial mode register (scsmr): set the o/ e bit to 0 when the ic card uses the direct convention or to 1 when it uses the inverse convention. select the on-chip baud rate generator clock source with the cks1 and cks0 bits (see section 15.3.5, clock). 2. setting the bit rate register (scbrr): set the bit rate. see section 15.3.5, clock, to see how to calculate the set value. 3. setting the serial control register (scscr): the tie, rie, te and re bits function as they do for the ordinary sci. see section 13, serial communication interface, for more information. the cke0 bit specifies the clock output. when no clock is output, set 0; when a clock is output, set 1. 4. setting the smart card mode register (scscmr): the sdir and sinv bits are both set to 0 for ic cards that use the direct convention and both to 1 when the inverse convention is used. the smif bit is set to 1 for the smart card interface. figure 15.4 shows sample waveforms for register settings of the two types of ic cards (direct convention and inverse convention) and their start characters. in the direct convention type, the logical 1 level is state z, the logical 0 level is state a, and communication is lsb first. the start character data is h'3b. the parity bit is even (from the smart card standards), and thus a 1. in the inverse convention type, the logical 1 level is state a, the logical 0 level is state z, and communication is msb first. the start character data is h'3f. the parity bit is even (from the smart card standards), and thus a 0, which corresponds to state z. only data bits d7?0 are inverted by the sinv bit. to invert the parity bit, set the o/ e bit in scsmr to odd parity mode. this applies to both transmission and reception.
409 ds d0 d1 d2 d3 d4 d5 d6 d7 dp a (z) z z a z z z a a z (z) state a. direct convention (sdir, sinv, and o/ e e figure 15.4 waveform of start character 15.3.5 clock only the internal clock generated by the on-chip baud rate generator can be used as the communication clock in the smart card interface. the bit rate for the clock is set by the bit rate register (scbrr) and the cks1 and cks0 bits in the serial mode register (scsmr), and is calculated using the equation below. table 15.5 shows sample bit rates. if clock output is then selected by setting cke0 to 1, a clock with a frequency 372 times the bit rate is output from the sck0 pin. b = 1 where: n = value set in scbrr (0 n 255) b = bit rate (bit/s) p? = peripheral module operating frequency (mhz)* n = 0? (table 15.4)
410 table 15.4 relationship of n to cks1 and cks0 n cks1 cks0 000 101 210 311 table 15.5 examples of bit rate b (bit/s) for scbrr settings (n = 0) p (mhz) n 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8 2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5 note: the bit rate is rounded to two decimal places. calculate the value to be set in the bit rate register (scbrr) from the operating frequency and the bit rate. n is an integer in the range 0 n 255, specifying a smallish error. n = 1 1488 1 table 15.6 examples of scbrr settings for bit rate b (bit/s) (n = 0) (mhz) (9600 bits/s) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 n error n error n error n error n error n error n error 0 0.00 1 30.00 1 25.00 1 8.99 1 0.00 1 12.01 2 15.99
411 table 15.7 maximum bit rates for frequencies (smart card interface mode) p (mhz) maximum bit rate (bit/s) n n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 the bit rate error is found as follows: error(%) = ( 1) 1 table 15.8 shows the relationship between transmit/receive clock register set values and output states on the smart card interface. table 15.8 register set values and sck pin register value sck pin setting smif c/ a cke1 cke0 output state 1* 1 1000 port determined by setting of port register spb1io and spb1dt bits 1001 sck (serial clock) output state 2* 2 1100 low output low output state 1101 sck (serial clock) output state 3* 2 1110 high output high output state 1111 sck (serial clock) output state notes: 1. the sck output state changes as soon as the cke0 bit is modified. the cke1 bit should be cleared to 0. 2. the clock duty remains constant despite stopping and starting of the clock by modification of the cke0 bit.
412 15.3.6 data transmission and reception initialization: initialize the sci using the following procedure before sending or receiving data. initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode. figure 15.5 shows a flowchart of the initialization process. 1. clear te and re in the serial control register (scscr) to 0. 2. clear error flags fer/ers, per, and orer to 0 in the serial status register (scssr). 3. set the c/ a bit, parity bit (o/ e bit), and baud rate generator select bits (cks1 and cks0 bits) in the serial mode register (scsmr). at this time also clear the chr and mp bits to 0 and set the stop and pe bits to 1. 4. set the smif, sdir, and sinv bits in the smart card mode register (scscmr). when the smif bit is set to 1, the txd and rxd pins both switch from ports to sci pins and become high impedance. 5. set the value corresponding to the bit rate in the bit rate register (scbrr). 6. set the clock source select bits (cke1 and cke0 bits) in the serial control register (scscr). clear the tie, rie, te, re, mpie, and teie bits to 0. when the cke0 bit is set to 1, a clock is output from the sck0 pin. 7. after waiting at least 1 bit, set the tie, rie, te, and re bits in scscr. do not set the te and re bits simultaneously unless performing auto-diagnosis.
413 initialize clear te and re bits in scscr to 0 set value in scbrr clear scssr s fer/ers, per and orer flags to 0 wait set scscr s tie, rie, te, and re bits has a 1-bit interval elapsed? end (2) set scsmr s o/ e s cke1 and cke0 bits to the clock and clear tie, rie, te, re, mpie, and teie bits to 0 (6) (5) (4) (1) (7) no yes set scsmr's smif, sdir, and sinv bits figure 15.5 initialization flowchart (example)
414 serial data transmission: the handling procedures in the smart card mode differ from ordinary sci processing because data is retransmitted when an error signal is sampled during a data transmission. this results in the transmission processing flowchart shown in figure 15.6. 1. initialize the smart card interface mode as described in initialization above. 2. check that the fer/ers bit in scssr is cleared to 0. 3. repeat steps 2 and 3 until the tend flag in scssr is set to 1. 4. write the transmit data into sctdr, clear the tdre flag to 0 and start transmitting. the tend flag will be cleared to 0. 5. to transmit more data, return to step 2. 6. to end transmission, clear the te bit to 0. this processing can be interrupted. when the tie bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (txi) will be requested when the tend flag is set to 1 at the end of the transmission. when the rie bit is set to 1 and interrupt requests are enabled, a communication error interrupt (eri) will be requested when the ers flag is set to 1 when an error occurs in transmission. see interrupt operation below for more information.
415 start end transmission start transmission initialize write transmit data in sctdr and clear tdre flag in scssr to 0 (1) clear te bit in scscr to 0 (6) error handling (2) fer/ers = 0? tend = 1? yes yes yes yes no no all data transmitted? no tend = 1? no error handling fer/ers = 0? yes no (4) (5) (3) figure 15.6 transmission flowchart
416 serial data reception: the handling procedures in the smart card mode are the same as in ordinary sci processing. the reception processing flowchart is shown in figure 15.7. 1. initialize the smart card interface mode as described above in initialization and in figure 15.5. 2. check that the orer and per flags in scssr are cleared to 0. if either flag is set, clear both to 0 after performing the appropriate error handling procedures. 3. repeat steps 2 and 3 until the rdrf flag is set to 1. 4. read the receive data from scrdr. 5. to receive more data, clear the rdrf flag to 0 and return to step 2. 6. to end reception, clear the re bit to 0. this processing can be interrupted. when the rie bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (rxi) will be requested when the rdrf flag is set to 1 at the end of the reception. when an error occurs during reception and either the orer or per flag is set to 1, a communication error interrupt (eri) will be requested. see interrupt operation, below, for more information. the received data will be transferred to scrdr even when a parity error occurs during reception and per is set to 1, so this data can still be read.
417 start end reception start reception initialize write receive data from scrdr and clear rdrf flag in scssr to 0 (1) clear re bit in scscr to 0 (6) error handling (2) orer = 0 or per = 0? rdrf = 1? yes yes yes no no all data received? no (4) (5) (3) figure 15.7 reception flowchart (example)
418 switching modes: when switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization and setting re to 0 and te to 1. the rdrf, per, and orer flags can be used to check if reception is completed. when switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization and setting te to 0 and re to 1. the tend flag can be used to check if transmission is completed. interrupt operation: in the smart card interface mode, there are three types of interrupts: transmit-data-empty (txi), communication error (eri) and receive-data-full (rxi). in this mode, the transmit-end interrupt (tei) cannot be requested. set the tend flag in scssr to 1 to request a txi interrupt. set the rdrf flag in scssr to 1 to request an rxi interrupt. set the orer, per, or fer/ers flag in scssr to 1 to request an eri interrupt (table 15.9). table 15.9 smart card mode operating status and interrupt sources mode status flag mask bit interrupt source transmit mode normal tend tie txi error fer/ers rie eri receive mode normal rdrf rie rxi error per, orer rie eri 15.4 usage notes when the sci is used as a smart card interface, be sure that all criteria in sections 15.4.1 and 15.4.2 are applied. 15.4.1 receive data timing and receive margin in asynchronous mode in asynchronous mode, the sci runs on a basic clock with a frequency of 372 times the transfer rate. during reception, the sci samples the fall of the start bit using the base clock to achieve internal synchronization. receive data is latched internally on the rising edge of the 186th basic clock cycle (figure 15.8).
419 0 185 371 0 185 371 0 base clock receive data (rxd) synchro- nization sampling timing data sampling timing 186 clock cycles 372 clock cycles start bit d0 d1 figure 15.8 receive data sampling timing in smart card mode the receive margin is found from the following equation: for smart card mode: m = (0.5 ) 1 2n d 0.5 n (l 0.5)f (1 + f) where: m = receive margin (%) n = ratio of bit rate to clock (n = 372) d = clock duty (d = 0 to 1.0) l = frame length (l = 10) f = absolute value of clock frequency deviation using this equation, the receive margin when f = 0 and d = 0.5 is as follows: m = 1/2 % = %
420 15.4.2 retransmission (receive and transmit modes) retransmission by the sci in receive mode: figure 15.9 shows the retransmission operation in the sci receive mode. 1. when the received parity bit is checked and an error is found, the per bit in scssr is automatically set to 1. if the rie bit in scscr is enabled at this time, an eri interrupt is requested. be sure to clear the per bit before the next parity bit is sampled. 2. the rdrf bit in scssr is not set in the frame that caused the error. 3. when the received parity bit is checked and no error is found, the per bit in scssr is not set. 4. when the received parity bit is checked and no error is found, reception is considered to have been completed normally and the rdrf bit in scssr is automatically set to 1. if the rie bit in scscr is enabled at this time, an rxi interrupt is requested. 5. when a normal frame is received, the pin maintains a three-state status when it transmits the error signal. d0 ds d2 d1 d4 d3 d6 d5 dp de d7 d0 ds d2 d1 d4 d3 d6 d5 dp (de) d7 d0 ds d2 d1 d4 d3 nth transfer frame rdrf per 2 1 4 5 3 retransmitted frame transfer frame n + 1 figure 15.9 retransmission in sci receive mode
421 retransmission by the sci in transmit mode: figure 15.10 shows the retransmission operation in the sci transmit mode. 1. after transmission of one frame is completed, the fer/ers bit in scssr is set to 1 when a error signal is returned from the receiving side. if the rie bit in scscr is enabled at this time, an eri interrupt is requested. be sure to clear the fer/ers bit before the next parity bit is sampled. 2. the tend bit in scssr is not set in the frame that received the error signal that indicated the error. 3. the fer/ers bit in scsr is not set when no error signal is returned from the receiving side. 4. when no error signal is returned from the receiving side, the tend bit in scssr is set to 1 when the transmission of the frame that includes the retransmission is considered completed. if the tie bit in scscr is enabled at this time, a txi interrupt will be requested. d0 ds d2 d1 d4 d3 d6 d5 dp de d7 d0 ds d2 d1 d4 d3 d6 d5 dp (de) d7 d0 ds d2 d1 d4 d3 nth transfer frame tend fer/ers transfer from tdr to trs transfer from tdr to trs transfer from tdr to trs 1 2 4 3 retransmitted frame transfer frame n + 1 tdre figure 15.10 retransmission in sci transmit mode
423 section 16 i/o ports 16.1 overview the has an on-chip 8-bit general-purpose i/o port and an on-chip i/o port for the serial communication interface (sci). 16.1.1 features the general-purpose i/o port has the following features: ? direction of each bit of the 8-bit i/o port can be set independently ? when each bit is set for input mode, it is possible to set each bit for independent pull-up ? ports can be used as i/o ports or as data bus lines, for a maximum data bus width of 32 bits, by setting the porten bit in bus control register 2 (bcr2) the sci i/o port has the following features: ? when the i/o port is set to output and the sci is not enabled, data can be output. this allows transmission of the break status. sck pin control is also possible. ? the value of the rxd pin can be read at any time. this enables break detection. 16.1.2 block diagram figure 16.1 shows a block diagram of the 8-bit general-purpose i/o port. port7 (i/o)/d23 (i/o) port6 (i/o)/d22 port5 (i/o)/d21 port4 (i/o)/d20 port3 (i/o)/d19 port2 (i/o)/d18 port1 (i/o)/d17 port0 (i/o)/d16 8-bit port figure 16.1 8-bit i/o port
424 figures 16.2 to 16.4 show block diagrams of the sci i/o port. internal data bus serial clock output clock output enable sci * serial clock input clock input enable r spb1io sptrw reset c q q d r spb1dt sptrw reset md0/sck c d sptrw: sptr write sptrr: sptr read sptrr note: * signals that set the sck pin function to internal clock output or external clock input as specified by the cke0 and cke1 bits in scscr, and the c/ a bit in scsmr. figure 16.2 sci i/o port: md0/sck pin
425 internal data bus transmit enable sci serial transmit data r spb0io sptrw reset c q q d r spb0dt sptrw reset md1/txd c d sptrw: sptr write figure 16.3 sci i/o port: md1/txd pin sci serial receive data internal data bus sptrr md2/rxd sptrr: sptr read figure 16.4 sci i/o port: md2/rxd pin
426 16.1.3 pin configuration table 16.1 shows the pin configuration of the 8-bit general-purpose i/o port. table 16.1 pin configuration pin signal i/o function port 7 port7 i/o i/o port port 6 port6 i/o i/o port port 5 port5 i/o i/o port port 4 port4 i/o i/o port port 3 port3 i/o i/o port port 2 port2 i/o i/o port port 1 port1 i/o i/o port port 0 port0 i/o i/o port table 16.2 shows the pin configuration of the sci i/o port. table 16.2 pin configuration pin signal i/o function serial transmission txd o serial data transmission and break status transmission serial reception rxd i serial data reception and break status detection serial clock sck i/o serial clock input/output and i/o port note: these pins function as mode input pins md0?d2 after a power-on reset. they are made to function as serial pins by performing sci operation settings with the te, re, ckei, and cke0 bits in scscr and the c/ a bit in scsmr. break status transmission and detection can be performed by means of the sci? scsptr register.
427 16.1.4 register configuration table 16.3 shows the configuration of the two registers of the 8-bit general-purpose i/o port (pctr and pdtr) and the one register of the sci i/o port (scsptr). table 16.3 register configuration register symbol r/w initial value address access size port control register pctr r/w h'0000 h'ffffff76 16 port data register pdtr r/w undefined h'ffffff78 8 serial port register scsptr r/w undefined h'ffffff7c 8 note: initialized to h?0 except bit 2 and 0. bit 2 and 0 are undefined. 16.2 register descriptions 16.2.1 port control register (pctr) the port control register (pctr) is a 16-bit read/write register that controls the input/output direction and pull-up for each bit in the 8-bit port. as the initial value of the port data register (pdr) is undefined, all the bits in the 8-bit port should be set to output with pctr after writing a value to the pdtr register. pctr is initialized to h'0000 by a power-on reset. it is not initialized by a manual reset or in standby mode, and retains its contents. bit: 15 14 13 12 11 10 9 8 bit name: pb7 pup pb7 io pb6 pup pb6 io pb5 pup pb5 io pb4 pup pb4 io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 bit name: pb3 pup pb3 io pb2 pup pb2 io pb1 pup pb1 io pb0 pup pb0 io initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
428 bit 2n + 1 (n = 0?): port pull-up control (pbnpup): controls the pull-up of each bit in the 8-bit port by means of built-in resistors. this setting is valid even if the port pin is set to output by the pbnio bit. therefore, to avoid unnecessary power consumption and ensure the reliability of the chip, a pull-up setting should not be made when the corresponding port pin has been set to output. bit 2n + 1: pbnpup description 0 bit n (n = 0?) of the 8-bit port is pulled up. (initial value) 1 bit n (n = 0?) of the 8-bit port is not pulled up. bit 2n (n = 0?)?ort i/o control (pbndir): controls whether each bit of 8-bit port is an input or an output. bit 2n: pbnio description 0 bit n (n = 0?) of the 8-bit port is an input. (initial value) 1 bit n (n = 0?) of the 8-bit port is an output. 16.2.2 port data register (pdtr) the port data register (pdtr) is an 8-bit read/write register used as data latches for each bit of the 8-bit port. when a bit is set to be used as an output, the value written into pdtr is output from the external pin. when a value is read from pdtr, the external pin value sampled on the external bus clock is returned. pdtr is not initialized by a power-on reset or manual reset, or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w
429 16.2.3 serial port register (scsptr) the serial port register (scsptr) is an 8-bit register that the cpu can always read and write. it controls i/o and data of the port multiplexed with the serial communication interface (sci) pins. input data can be read from the rxd pin and output data can be transmitted to the txd pin; this controls breaks for serial transmission and reception. in addition, sck pin data reading and output data writing can be performed by means of bits 3 and 2. all scsptr bits except bits 2 and 0 are initialized to 0 by a power-on reset; the value of bits 2 and 0 is undefined. scsptr is not initialized by a manual reset or in standby mode. bit: 7 6 5 4 3 2 1 0 bit name: spb1io spb1dt spb0io spb0dt initial value: 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w bits 7 to 4?eserved: these bits are always read as 0. the write value should always be 0. bit 3?erial port clock port i/o (spb1io): specifies serial port sck pin input/output. when the sck pin is actually set as a port output pin and outputs the value set by the spb1dt bit, the c/ a bit in scsmr and the cke1 and cke0 bits in scscr should be cleared to 0. bit 3: spb1io description 0 the spb1io value is not output to the sck pin. (initial value) 1 the spb1io bit value is output to the txd pin. bit 2?erial port clock port data (spb1dt): specifies the serial port sck pin input/output data. input or output is specified by the spb1io bit (see the description of spb1io for details). when output is specified, the value of the spb1dt bit is output to the sck pin. the sck pin value is read from the spb1dt bit regardless of the value of the spb1io bit. the initial value of this bit after a power-on reset is undefined. bit 2: spb1dt description 0 i/o data level is low. (initial value) 1 i/o data level is high.
430 bit 1?erial port break i/o (spb0io): specifies the serial port txd pin output condition. when the txd pin is actually set as a port output pin and outputs the value set by the spb0dt bit, the te bit in scscr should be cleared to 0. bit 1: spb0io description 0 the spb0dt bit value is not output to the txd pin. (initial value) 1 the spb0dt bit value is output to the txd pin. bit 0?erial port break data (spb0dt): specifies serial port rxd pin input data and txd pin output data. the txd pin output condition is set with the spb0io bit (see the description of spb0io above). when the txd pin is set as an output, the value of the spb0dt bit is output to the txd pin. the rxd pin value is always read from the spb0dt bit, regardless of the value of the spb0io bit. the initial value of this bit after a power-on reset is undefined. bit 0 : spb0dt description 0 i/o data level is low. (initial value) 1 i/o data level is high.
431 section 17 electrical characteristics 17.1 absolute maximum ratings table 17.1 absolute maximum ratings item symbol ratings units power supply voltage v cc ?.3 to 4.6 v input voltage v in ?.3 to v cc + 0.3 v operating temperature t opr ?0 to + 75 c storage temperature t stg ?5 to + 125 c note: operating the sh7718r above maximum ratings can damage or destroy it.
432 17.2 dc characteristics table 17.2 dc characteristics (t a = ?0 to + 75?) item symbol min typ max unit remarks power supply voltage v cc 3.15 3.3 3.6 v in normal operation, sleep mode, and standby mode current normal operation i cc 120* 1 200 * 1 ma *1 v cc = 3.3 v i?= 100 mhz b?= 50 mhz in sleep mode 75* 2 100 * 2 *2 b?= 60 mhz p?= 30 mhz *3 v cc = 3.3 v/t a = 25? in standby mode 0.1* 3 1* 3 ma input reset, nmi v ih v cc 0.9 v cc + 0.3 v voltage breq, irl3?rl0, v cc ?0.5 v cc + 0.3 standby mode md5?d0 v cc ?0.7 v cc + 0.3 normal operation extal, ckio v cc ?0.7 v cc + 0.3 other input pins 2.0 v cc + 0.3 reset, nmi v il ?.3 v cc 0.1 breq, irl3?rl0, ?.3 0.5 standby mode md5?d0 ?.3 v cc 0.2 normal operation other input pins ?.3 v cc 0.2 input leak current all input pins |l in | 1.0 av in = 0.5 to v cc ?0.5 v three- state leak current i/o, output, all pins (off condition) |i tsi | 1.0 av in = 0.5 to v cc ?0.5 v
433 table 17.2 dc characteristics (t a = ?0 to + 75?) (cont) item symbol min typ max unit remarks output voltage all output pins v oh 2.4 v v cc = 3.0 v, i oh = ?00 a 2.0 v cc = 3.0 v, i oh = ? ma v ol 0.55 v cc = 3.6 v, i ol = 1.6 ma pull-up resistance port pins r puii 30 60 120 k ? terminal capaci- tance all pins c 20 pf notes: 1. regardless of whether pll or rtc is used, connect v cc (pll), v cc (rtc) to v cc , and v ss (pll), v ss (rtc) to v ss . 2. current condition is v ih min = v cc ?0.5 v, v il max = 0.5 v, and all output pins unloaded. table 17.3 permissible output current values (v cc = 3.3 ?0.3 v, t a = ?0 to + 75?) item symbol min typ max unit permissible output low current (per pin) i ol 2.0 ma permissible output low current (total) i ol 120 permissible output high current (per pin) ? oh 2.0 permissible output high current (total) (? oh ) 40 note: to ensure reliability, output current must not exceed the maximum values listed. 17.3 ac characteristics input for the lsi should, as a rule, be clock synchronous. keep to the setup and hold times for each input signal unless otherwise directed. table 17.4 lsi clock values (t a = ?0 to + 75?) item symbol max unit operating cpu, cache, tlb f 100 mhz frequency external bus 60 peripheral modules 33.3
434 17.3.1 clock timing table 17.5 clock timing (v cc = 3.15?.6 v, t a = ?0 to + 75?, maximum external bus operating frequency: 60 mhz) item symbol min max unit figure extal clock input frequency f ex 5 60 mhz 17.1 extal clock input cycle time t excyc 16.7 200 ns extal clock input low-level pulse width t exl 4* 1 or 10* 2 ?s extal clock input high-level pulse width t exh 4* 1 or 10* 2 ?s extal clock input rise time t exr 2 ns extal clock input fall time t exf 2 ns ckio clock frequency (input) f cki 16 60 mhz 17.2 ckio clock cycle time (input) t ckicyc 16.7 62.5 ns ckio clock low-level pulse width (input) t ckil 4 ns ckio clock high-level pulse width (input) t ckih 4 ns ckio clock rise time (input) t ckir 2 ns ckio clock fall time (input) t ckif 2 ns ckio clock output frequency (output) f op 16 60 mhz 17.3 ckio clock cycle time (output) t cyc 16.7 62.5 ns ckio clock low-level pulse width (output) t ckol 3 ns ckio clock high-level pulse width (output) t ckoh 3 ns ckio clock rise time (output) t ckor 5 ns ckio clock fall time (output) t ckof 5 ns power-on oscillation settling time t osc1 10 ms 17.4 power-on oscillation settling time/mode setting t oscmd 10 ms breq reset hold time t breqrh 0 ns reset set-up time t ress 20 ns breq set-up time t breqs 20 ns md reset hold time t mdrh 20 ns reset assert time t resw 20 tcyc 17.4, 17.5 standby return oscillation settling time 1 t osc2 10 ms 17.5 standby return oscillation settling time 2 t osc3 10 ms 17.6 standby return oscillation settling time 3 t osc4 11 ms 17.7 pll synchronization settling time t pll 100 s 17.8, 17.9, 17.10 irl interrupt decision time (using rtc and in standby mode) t irlstb 100 s 17.10 notes: 1. pll circuit 2 in operation. 2. pll circuit 2 not in operation.
435 t exh t exf t exr t exl t excyc v ih v ih v ih 1/2 v cc 1/2 v cc v il v il extal* (input) note: * the clock input from the extal pin. figure 17.1 extal clock input timing t ckih t ckif t ckir t ckil t ckicyc v ih 1/2 v cc 1/2 v cc v ih v il v ih v il ckio (input) figure 17.2 ckio clock input timing t cyc t ckol t ckoh v ih 1/2v cc ckio (output) 1/2v cc t ckor t ckof v oh v ol v ol v oh figure 17.3 ckio clock output timing
436 v cc min t resw t ress t osc1 t breqrh t breqs t mdrh t oscmd v cc reset breq md0 md2 ckio, internal clock stable oscillation note: oscillation settling time when built-in oscillator is used figure 17.4 power-on oscillation settling time ckio, internal clock stable oscillation standby t osc2 t resw res note: oscillation settling time when built-in oscillator is used figure 17.5 standby return oscillation settling time (return by reset)
437 ckio, internal clock stable oscillation standby t osc3 nmi note: oscillation settling time when built-in oscillator is used figure 17.6 standby return oscillation settling time (return by nmi) ckio, internal clock stable oscillation standby t osc4 irl3 irl0 note: oscillation settling time when built-in oscillator is used figure 17.7 standby return oscillation settling time (return by irl3 irl0 )
438 extal input or ckio input stable input clock reset or nmi interrupt request stable input clock normal normal standby pll output, ckio output internal clock status 0 status 1 pll synchronization note: pll oscillation settling time when clock is input from extal pin or ckio pin t pll pll synchronization figure 17.8 pll synchronization settling time in case of reset or nmi interrupt extal input or ckio input stable input clock irl (3C0) interrupt request stable input clock normal normal pll output, ckio output internal clock status 0 status 1 note: pll oscillation settling time when clock is input from extal pin or ckio pin t pll pll synchronization t irlstb standby pll synchronization figure 17.9 pll synchronization settling time in case of irl interrupt
439 extal input or on-chip oscillator output ckoen ckio pll1 output internal clock note: pll oscillation settling time when output clock is controlled by clock mode 0 2 t pll t pll pll synchronization pll synchronization pll synchronization figure 17.10 pll synchronization settling time in case of ckoen bit manipulation
440 17.3.2 control signal timing table 17.6 control signal timing (v cc = 3.15?.6 v, t a = ?0 to + 75?) ?0* 2 item symbol min max unit figure reset pulse width t resw 20 tcyc 17.11, 17.13, reset setup time t ress 23 ns 17.15 reset hold time t resh 2 ns breq setup time t breqs 12 ns breq hold time t breqh 3 ns breq reset setup time t breqrs 17 ns breq reset hold time t breqrh 16 ns md reset setup time t mdrs 20 tcyc 17.12 md reset hold time t mdrh 16 ns nmi setup time* 1 t nmis 15 ns 17.13 irl3 irl0 setup time* 1 t irls 10 ns nmi hold time t nmih 4 ns irl3 irl0 hold time t irlh 4 ns irqout delay time t irqod 12 ns 17.14 back delay time t backd 12 ns 17.15, 17.16 status1, status0 delay time t std 16 ns bus tri-state delay time 1 t boff1 016ns bus tri-state delay time 2 t boff2 016ns bus buffer on time 1 t bon1 016ns bus buffer on time 2 t bon2 016ns notes: 1. reset , nmi, and irl3 to irl0 are asynchronous. changes are detected at the clock fall when the setup shown is used. when the setup cannot be used, detection can be delayed until the next clock fall. 2. upper limit of external bus clock is 60 mhz.
441 ckio reset breq t ress t ress t resw t breqrs t breqs t breqrh figure 17.11 manual reset input timing t mdrs t mdrh reset md0 md5 figure 17.12 mode input timing
442 ckio reset t resh t ress v ih v il nmi t nmih t nmis v ih v il irl3 irl0 t irlh t irls v ih v il figure 17.13 interrupt signal input timing c kio t irqod t irqod i rqout figure 17.14 irqout timing
443 ckio breq back rd , rd/ wr , ras , cas , csn , wen , bs a25 a0, d31 d0 t backd t boff2 t boff1 t bon1 t backd t bon2 t breqh t breqh t breqs t breqs figure 17.15 bus release timing ckio t std t boff2 t boff1 t std t bon2 t bon1 normal mode standby mode normal mode status 0 status 1 rd , rd/ wr , ras , cas , csn , wen , bs a25 a0, d31 d0 figure 17.16 pin drive timing for standby mode
444 17.3.3 ac bus timing specifications table 17.7 bus timing (conditions: clock mode 0/1/2/7, v cc = 3.15?.6 v, t a = ?0 to + 75?) ?0 * 1 item symbol min max unit figure address delay time t ad 1.5 13 ns 17.17?7.30, 17.34?7.41, 17.44?7.48, 17.52?7.58 address setup time t as 0 ns 17.23?7.30, 17.45?7.48 address hold time t ah 0 ns 17.17?7.30, 17.45?7.48 bs delay time t bsd 12 ns 17.17?7.30, 17.34?7.41, 17.45?7.48, 17.52?7.58 cs delay time 1 t csd1 1.5 12 ns 17.17?7.30, 17.34?7.44, 17.52?7.58 cs delay time 2 t csd2 12 ns 17.17?7.22 read write delay time t rwd 1.5 12 ns 17.17?7.48, 17.52?7.56 read write setup time t rws 0 ns 17.45?7.48 read write hold time t rwh 0 ns 17.17?7.30, 17.45?7.48 read strobe delay time t rsd 12 ns 17.17?7.22, 17.52?7.56 read data setup time 1 t rds1 12 ns 17.17?7.26, 17.45?7.48, 17.52?7.58 read data setup time 2 t rds2 8 ns 17.27?7.30, 17.34?7.37, 17.41 read data hold time 1 t rdh1 0 ns 17.17?7.26, 17.45?7.48, 17.52?7.58 read data hold time 2 t rdh2 3 ns 17.27?7.30, 17.34?7.37, 17.41 write enable delay time t wed 12 ns 17.17?7.19, 17.45?7.48, 17.52, 17.53 write data delay time 1 t wdd1 15 ns 17.17?7.19, 17.52, 17.53, 17.56?7.58 write data delay time 2 t wdd2 13 ns 17.23?7.30, 17.38?7.40, 17.45?7.48, 17.58 write data setup time t wds 0 ns 17.23?7.30, 17.45?7.48 write data hold time 1 t wdh1 0 ns 17.17?7.19, 17.23?7.30, 17.45?7.48, 17.52?7.57 write data hold time 2 t wdh2 1.5 ns 17.38?7.40 write data hold time 3 t wdh3 0 ns 17.17?7.19, 17.23?7.30, 17.45?7.48, 17.58 write data hold time 4 t wdh4 0 ns 17.52, 17.53, 17.56?7.58
445 table 17.7 bus timing (conditions: clock mode 0/1/2/7, v cc = 3.15?.6 v, t a = ?0 to + 75?) (cont) ?0* 1 item symbol min max unit figure wait setup time * 2 t wts 12 ns 17.18?7.22, 17.53, 17.55, 17.57, 17.58 wait hold time * 2 t wth 4 ns 17.18?7.22, 17.53, 17.55, 17.57, 17.58 ras delay time 1 t rasd1 13 ns 17.23?7.33 ras delay time 2 t rasd2 1.5 13 ns 17.27?7.30, 17.34?7.44 cas delay time 1 t casd1 13 ns 17.23?7.33 cas delay time 2 t casd2 1.5 13 ns 17.34?7.44 dqm delay time t dqmd 1.5 12 ns 17.34?7.41 cke delay time t cked 12 ns 17.43 ce delay time t ced 13 ns 17.45?7.48 oe , rfsh delay time t oed 13 ns 17.45?7.51 iciord delay time t icrsd 12 ns 17.56?7.58 iciowr delay time t icwsd 12 ns 17.56?7.58 iois16 setup time t io16s 12 ns 17.57, 17.58 iois16 hold time t io16h 4 ns 17.57, 17.58 notes: 1. upper limit of external bus clock is 60 mhz. 2. wait is a synchronous signal. operation cannot be guaranteed if the setup times shown here are not observed.
446 table 17.8 bus timing (conditions: clock mode 3/4, v cc = 3.15?.6 v, t a = ?0 to + 75?) item symbol min max unit figure address delay time t ad 1.5 20 ns 17.17?7.30, 17.34?7.41, 17.44?7.48, 17.52?7.58 address setup time t as 0 ns 17.23?7.30, 17.45?7.48 address hold time t ah 20 ns 17.17?7.30, 17.45?7.48 bs delay time t bsd 19 ns 17.17?7.30, 17.34?7.41, 17.45?7.48, 17.52?7.58 cs delay time 1 t csd1 1.5 19 ns 17.17?7.30, 17.34?7.44, 17.52?7.58 cs delay time 2 t csd2 20 ns 17.17?7.22 read write delay time t rwd 1.5 19 ns 17.17?7.48, 17.52?7.56 read write setup time t rws 0 ns 17.45?7.48 read write hold time t rwh 0 ns 17.17?7.30, 17.45?7.48 read strobe delay time t rsd 20 ns 17.17?7.22, 17.52?7.56 read data setup time 1 t rds1 12 ns 17.17?7.26, 17.45?7.48, 17.52?7.58 read data setup time 2 t rds2 12 ns 17.27?7.30, 17.34?7.37, 17.41 read data hold time 1 t rdh1 0 ns 17.17?7.26, 17.45?7.48, 17.52?7.58 read data hold time 2 t rdh2 8 ns 17.27?7.30, 17.34?7.37, 17.41 write enable delay time t wed 20 ns 17.17?7.19, 17.45?7.48, 17.52, 17.53 write data delay time 1 t wdd1 25 ns 17.17?7.19, 17.52, 17.53, 17.56?7.58 write data delay time 2 t wdd2 19 ns 17.23?7.30, 17.38?7.40, 17.45?7.48, 17.58 write data setup time t wds 0 ns 17.23?7.30, 17.45?7.48 write data hold time 1 t wdh1 0 ns 17.17?7.19, 17.23?7.30, 17.45?7.48, 17.52?7.57 write data hold time 2 t wdh2 1.5 ns 17.38?7.40 write data hold time 3 t wdh3 0 ns 17.17?7.19, 17.23?7.30, 17.45?7.48, 17.58 write data hold time 4 t wdh4 0 ns 17.52, 17.53, 17.56?7.58
447 table 17.8 bus timing (conditions: clock mode 3/4, v cc = 3.15?.6 v, t a = ?0 to + 75?) (cont) item symbol min max unit figure wait setup time t wts 12 ns 17.18?7.22, 17.53, 17.55, 17.57, 17.58 wait hold time t wth 8 ns 17.18?7.22, 17.53, 17.55, 17.57, 17.58 ras delay time 1 t rasd1 20 ns 17.23?7.33 ras delay time 2 t rasd2 1.5 19 ns 17.27?7.30, 17.34?7.44 cas delay time 1 t casd1 20 ns 17.23?7.33 cas delay time 2 t casd2 1.5 19 ns 17.34?7.44 dqm delay time t dqmd 1.5 19 ns 17.34?7.41 cke delay time t cked 19 ns 17.43 ce delay time t ced 20 ns 17.45?7.48 oe , rfsh delay time t oed 20 ns 17.45?7.51 iciord delay time t icrsd 20 ns 17.56?7.58 iciowr delay time t icwsd 20 ns 17.56?7.58 iois16 setup time t io16s 12 ns 17.57, 17.58 iois16 hold time t io16h 8 ns 17.57, 17.58
448 17.3.4 basic timing t 1 ckio a25 a0 csn rd/ wr rd (read) d31 d0 (read) wen (write) d31 d0 (write) bs t 2 t ad t ah t ad t csd1 t rwd t rsd t csd2 t wed t wdd1 t rds1 t bsd t bsd t rdh1 t rdh1 t wed t rsd t ah t rwh t rwd t wdh1 t rwh t rwh t ah t wdh3 figure 17.17 basic bus cycle (no wait)
449 t 1 t w t 2 ckio a25 a0 csn rd/ wr rd (read) d31 d0 (read) wen (write) d31 d0 (write) bs wait t ad t ad t rwd t rwh t ah t ah t rsd1 t csd1 t wed1 t wdd1 t bsd t wts t wth t bsd t rds1 t csd2 t wed t rsd t rdh1 t rdh1 t rwd t ah t rwh t wdh3 t wdh1 t rwh figure 17.18 basic bus cycle (1 wait)
450 t 1 t w t w t 2 ckio a25 a0 csn rd/ wr rd (read) d31 d0 (read) wen (write) d31 d0 (write) bs wait t ad t ad t rwd t rsd1 t wed t wdd1 t wts t wth t bsd t bsd t rds1 t wts t wth t csd1 t csd2 t rsd t wed t rdh1 t ah t rwh t rdh1 t ah t rwh t rwd t rwh t ah t wdh3 t wdh1 figure 17.19 basic bus cycle (external wait)
451 17.3.5 burst rom timing ckio a25 a4 a3 a0 csn rd/ we rd d31 d0 bs wait t ad t ad t ad t ad t csd1 t rwd t bsd t bsd t ah t bsd t bsd t csd2 t rsd t rds1 t wts t wth t rds t rsd t 1 t b2 t b1 t b2 t b1 t b2 t b1 t 2 t rsd t rdh1 t rsd t ah t rdh1 t rwh t ah t rwh t rwd t rdh1 note: in the write cycle, the basic bus cycle is performed. figure 17.20 burst rom bus cycle (no wait)
452 ckio a25 a4 a3 a0 csn rd/ we rd d31 d0 bs wait t ad t ad t ad t csd1 t rwh t rwd t rsd t rsd t rdh1 t rdh1 t rdh1 t rds1 t bsd t bsd t bsd t bsd t wts t wth t wts t wth t wts t wth t wts t wth t 1 t w t w t b2 t b1 t b2 t w t 2 t 2 t csd2 t rds1 t rsd t rsd t ah t ah t rdh1 t ah t rsd t rwd t rwh note: in the write cycle, the basic bus cycle is performed. figure 17.21 burst rom bus cycle (2 waits)
453 ckio a25 a4 a3 a0 csn rd/ we rd d31 to d0 bs wait t 1 t w t w t b2 t b1 t 2 t bw t ad t ad t csd1 t csd2 t rwd t rwh t rdh1 t ah t ah t rwd t rsd t rsd1 t ah t ad t bsd t bsd t wts t wth t wts t wth t wts t wth t wts t wth t bsd t bsd t rds1 t rdh1 t rsd t rdh1 t rwh t rsd1 note: in the write cycle, the basic bus cycle is performed. t rds figure 17.22 burst rom bus cycle (external wait input)
454 17.3.6 dram timing t ad t ad t bsd t csd1 t csd1 t bsd t rds1 t r t c1 t c2 (t pc ) ckio a25 to a16 a15 to a0 rd/ wr ras casxx d31 d0 (read) d31 d0 (write) cs2 or cs3 bs row address t ad t rwd t ah t ad t as t as row address column address t rasd1 t casd1 t wds t rasd1 t rwh t ah t rwh t ah t casd1 t rdh1 t wdd2 t rwd t wdh3 t wdh1 figure 17.23 dram bus cycle (rcd = 0, anw = 1, tpc = 0)
455 t wdh1 t wdh3 t bsd t csd1 t csd1 t bsd t rds1 t r t rw t rw t c1 t cw t c2 (t pc )(t pc ) ckio a25 to a16 a15 to a0 rd/ wr ras casxx d31 d0 (read) d31 d0 (write) cs2 or cs3 bs t ad t ad t ad t as t ad t as row address row address column address t rasd1 t rasd1 t rwh t ah t rwh t ah t casd1 t casd1 t wds t rwd t ah t rdh1 t wdd2 t rwd figure 17.24 dram bus cycle (rcd = 2, anw = 2, tpc = 1)
456 t r ckio a25 a16 a15 a0 rd/ wr ras casxx d31 d0 (read) d31 d0 (write) cs2 or cs3 bs t c1 t c2 t c1 t c2 t c1 t c2 t c1 t c2 (t pc ) t ad row address t ad column address column address column address column address t bsd t bsd t wdh3 t wdh3 t csd1 t csd1 t rasd1 t rwh t ah t rasd1 t casd1 t casd1 t casd1 t ah t rds1 t wds t rdh1 t casd1 t rwd t ah t ad t ad t ad t as t as row address t rwd t rds1 t rdh1 t wdd2 t rwh t wdd2 t wdh1 figure 17.25 dram burst bus cycle (rcd = 0, anw = 1, tpc = 0)
457 ckio rd/ wr d31 d0 (read) d31 d0 (write) ras casxx bs cs2 or cs3 a25 a16 a15 a0 t r t ad row address t ad t rwd t rwh t rdh1 t rdh1 t rds1 t wds t ah t ah t rwh t wdh3 t wdh1 t wdh3 t wdd2 t csd1 t bsd t bsd t csd1 t as t as t ad t c2 (t pc ) t rasd1 t cw t c1 t c2 t cw t c1 t rw t rw t ah t rwd t rasd1 t casd1 t rds1 t ad t ad row address t casd1 t casd1 t wdd2 column address column address row address figure 17.26 dram burst bus cycle (rcd = 2, anw = 2, tpc = 0)
458 ckio rd/ wr d31 d0 (read) d31 d0 (write) ras casxx bs cs2 or cs3 a25 a16 t r t c1 t c2 (t pc ) t ad t ad t as t ad t rasd1 t ad t as t ah t rwd t ah a15 a0 t rwh t rwd t rasd2 t casd1 t casd1 t wdh3 t wdh1 t rdh2 t rds2 t wdd2 t bsd t bsd t csd1 t csd1 t wds row address row address column address figure 17.27 dram bus cycle (edo mode, rcd = 0, anw = 1, tpc = 0)
459 ckio rd/ wr d31 d0 (read) d31 d0 (write) ras casxx bs cs2 or cs3 a25 a16 a15 a0 t r t rw t rw t c1 t cw t c2 (t pc ) (t pc ) t rwh t rwd row address t ad t ad t rwd t rasd1 t ah t ad t as t ad t ah t as t rasd2 t casd1 t wdh3 t wdh1 t wds t rds2 t rdh2 t casd1 t bsd t bsd t csd1 t csd1 row address column address t wdd2 figure 17.28 dram bus cycle (edo mode, rcd = 2, anw = 2, tpc = 1)
460 ckio rd/ wr d31 d0 (read) d31 d0 (write) ras casxx bs cs2 or cs3 a25 a16 a15 a0 t r t ad row address column address column address t ad t ad t rwd t wdh3 t rds2 t rds2 t wds t rdh2 t wdh3 t csd1 t bsd t bsd t csd1 t as t as t ah t ah t ah t rwh t ad t ad t c2 (t pc ) t wdh1 t wdd2 t c1 t c2 t c1 t c2 t c1 t c2 t c1 t rwd t rasd1 t casd1 t casd1 t casd1 t casd1 row address t rasd2 t rdh2 t wdd2 column address column address row address figure 17.29 dram burst bus cycle (edo mode, rcd = 0, anw = 1, tpc = 0)
461 ckio rd/ wr d31 d0 (read) d31 d0 (write) ras casxx bs cs2 or cs3 a25 a16 a15 a0 t r row address row address t c2 (t pc ) t cw t c1 t c2 t cw t c1 t rw t rw t ad t ad t ah t ah t rdh2 t wdh3 t wdd2 t wdh1 t wdh3 t rds2 t rwh t rwd t ah t ad t as t ad t ad t as t rwd t rasd1 t rasd2 t rdh2 t rds2 t casd1 t casd1 t wdd2 t wds t bsd t csd1 t csd1 t bsd t casd1 column address column address figure 17.30 dram burst bus cycle (edo mode, rcd = 2, anw = 2, tpc = 0)
462 t rc t rr1 t rrw t rr2 t rasd1 t rasd1 t casd1 t casd1 t rwd (high) (t pc ) ckio rd/ wr ras casxx cs2 or cs3 figure 17.31 dram cas-before-ras refresh cycle (tras = 0, tpc = 0) t rc t rr1 t rrw t rrw t rrw t rrw t rr2 t rasd1 t rasd1 t casd1 t casd1 t rwd (high) (t pc )(t pc )(t pc ) ckio rd/ wr ras casxx cs2 or cs3 figure 17.32 dram cas-before-ras refresh cycle (tras = 3, tpc = 2)
463 t rc t rr1 t rrw t sr1 t sr1 t sr2 (t pc ) t rasd1 t rasd1 t casd1 t casd1 t rwd (high) (t pc ) ckio rd/ wr ras casxx cs2 or cs3 figure 17.33 dram self-refresh cycle (tpc = 0)
464 17.3.7 synchronous dram timing t r t c1 t c2 (t pc ) ckio a25 a16 a12 or a10 a15 a0 rd/ wr ras cas dqmxx d31 d0 bs cke t csd1 t csd1 t rasd2 t rasd2 t casd2 t casd2 t dqmd t dqmd t bsd t bsd (high) t rdh2 t rds2 csn t ad t ad row address t ad t ad t ad t ad row address row address column address t ad t ad read a command t rwd t rwd figure 17.34 synchronous dram read bus cycle (rcd = 0, cas latency = 1, tpc = 0)
465 ckio a25 a16 a12 or a10 a15 a0 rd/ wr ras cas dqmxx d31 d0 bs cke t csd1 t csd1 t rasd2 t rasd2 t casd2 t casd2 t dqmd t dqmd t bsd t bsd (high) t rdh2 t rds2 csn t ad t ad t ad t ad t ad t ad t ad t ad t rwd t rwd t r t rw t rw t c1 t cw t d1 (t pc )(t pc ) column address row address row address row address read a command figure 17.35 synchronous dram read bus cycle (rcd = 2, cas latency = 2, tpc = 1)
466 ckio a25 a16 a12 or a10 a15 a0 rd/ wr ras cas dqmxx d31 d0 bs cke csn t r t c1 t c2 /t d1 t c3 /t d2 t c4 /t d3 t d4 (t pc )(t pc ) t ad t ad t ad t ad t ad t ad row address read a command t ad t ad t ad column address (1 4) read command row address row address t csd1 t csd1 t rwd t rwd t casd2 t casd2 t dqmd t dqmd t bsd t bsd t rdh2 t rds2 t rdh2 t rds2 t rasd2 t rasd2 (high) figure 17.36 synchronous dram read bus cycle (burst read (single read 4), rcd = 0, cas latency = 1, tpc = 1)
467 t r t rw t c1 t c2 t c3 t c4 /t d1 t d2 t d3 t d4 (t pc ) ckio a25 a16 a12 or a10 a15 a0 rd/ wr ras cas dqmxx d31 d0 (read) bs cke csn (high) t ad t ad t ad t ad t ad row address row address row address t ad t ad t ad t ad t ad t rwd t rwd read command t csd1 t csd1 t casd2 t casd2 t dqmd t dqmd t bsd t bsd t rdh2 t rds2 t rdh2 t rds2 t rasd2 t rasd2 column address (1 4) figure 17.37 synchronous dram read bus cycle (burst read (single read 4), rcd = 1, cas latency = 3, tpc = 0)
468 t r t c1 (t rwl ) (tpc) ckio a25 a16 a12 or a10 a15 a0 rd/ wr ras cas dqmxx d31 d0 bs cke t csd1 t csd1 t rasd2 t rasd2 t casd2 t casd2 t dqmd t dqmd t bsd t bsd (high) t wdh2 t wdd2 csn t ad t ad row address t ad t ad t ad t ad row address row address t ad t ad write a command t rwd t rwd t rwd column address figure 17.38 synchronous dram write bus cycle (rcd = 0, tpc = 0, trwl = 0)
469 ckio a25 a16 a12 or a10 a15 a0 rd/ wr ras cas dqmxx d3 d0 bs cke csn t r t rw t rw t c1 (t rwl )(t rwl )(t pc ) (t pc ) t csd1 t csd1 t rasd2 t rasd2 t casd2 t casd2 t dqmd t dqmd t bsd t bsd (high) t wdh2 t wdd2 t ad t ad row address t ad t ad t ad t ad row address t ad t ad t ad t rwd t rwd t rwd t ad row address write a command column address figure 17.39 synchronous dram write bus cycle (rcd = 2, tpc = 1, trwl = 1)
470 ckio a25 a16 a12 or a10 a15 a0 rd/ wr ras cas dqmxx d31 d0 bs cke csn t r t c1 t c2 t c3 t c4 (t rwl )(t pc )(t pc ) t ad t ad t ad t ad t ad t ad write command row address write a command t ad t ad t ad column address (1 4) row address t csd1 t csd1 t casd2 t casd2 t dqmd t dqmd t bsd t bsd t wdh2 t wdd2 t wdd2 t rasd2 t rasd2 t rwd t rwd t rwd row address (high) figure 17.40 synchronous dram write bus cycle (burst mode (single write 4), rcd = 0, tpc = 1, trwl = 0)
471 t r t rw t c1 t c2 t c3 t c4 (t rwl ) (t pc ) ckio a25 a16 a12 or a10 a15 a0 rd/ wr ras cas dqmxx d31 d0 bs cke csn (high) t ad t ad t ad t ad row address row address row address t ad t ad t ad t ad t rwd t rwd t rwd write command t ad t csd1 t csd1 t casd2 t casd2 t dqmd t dqmd t bsd t bsd t wdd2 t wdd2 t rasd2 t rasd2 column address (1 4) write a command t wdh2 figure 17.41 synchronous dram write bus cycle (burst mode (single write 4), rcd = 1, tpc = 0, trwl = 0)
472 ckio cke t rr t rrw t rrw (t pc ) (t pc ) (high) t csd1 t csd1 t rasd2 t rasd2 t casd2 t casd2 t rwd rd/ wr ras cas csn figure 17.42 synchronous dram auto-refresh cycle (tras = 1, tpc = 1)
473 ckio cke t rs1 (t rs2 ) (t rs2 ) t rs3 (t pc ) (t pc ) t csd1 t csd1 t cked t cked t rasd2 t rasd2 t casd2 t casd2 t rwd rd/ wr ras cas csn figure 17.43 synchronous dram self-refresh cycle (tpc = 0)
474 ckio a13 or a11 a12 or a10 a11 a2 or a9 a2 rd/ wr (high) ras casxx d31 d0 cke csn t rp1 t rp2 t rp3 t rp4 t mw1 t mw2 t mw3 t mw4 t ad t ad t ad t ad t ad t ad t csd1 t ad t ad t ad t ad t ad t rasd2 t rasd2 t rasd2 t rasd2 t csd1 t rwd t rwd t rwd t casd2 t casd2 figure 17.44 synchronous dram mode register write cycle
475 17.3.8 pseudo-sram timing t ad t as t ad t wdh3 t bsd t bsd t oed t wed t wds t rds1 a25 a0 rd/ wr ce oe / rfsh (read) d31 d0 (read) wen (write) d31 d0 (write) bs t rwd t r t c1 t c2 (t pc ) ckio t rws t ced t rdh1 t rwd t rwh t ced t ah t oed t rwh t ah t wed t rwh t ah t wdd2 t wdh1 figure 17.45 pseudo-sram bus cycle (rcd = 0, a3w = 1, tpc = 0)
476 t ad t as t ad t wds t wdh3 t bsd t bsd t oed t rds1 a25 a0 rd/ wr ce oe / rfsh (read) wen (write) d31 d0 (read) d31 d0 (write) bs ckio t r t rw t c1 t c1w t c1w t c2 (t pc ) t rdh1 t wed t wed t rwh t ah t rwd t rws t rwd t ced t oed t ah t ced t ah t rwh t rwh t wdd2 t wdh1 figure 17.46 pseudo-sram read cycle (rcd = 1, a3w = 3, tpc = 0)
477 ckio a25 a4 rd/ wr oe / rfsh (read) ce wen (write) d31 d0 (read) d31 d0 (write) bs t ad t as t r t c1 t c2 t c1 t c2 t c1 t c2 t c1 t c2 (t pc ) t ad t bsd t bsd t bsd t bsd t ced t ced t ah t oed t oed t oed t ah t wed t as t as t wed t wds t wdh3 t wdh3 t rds1 t rds1 t rwd t rws t rwd t wed t wed t oed t ah t wdd2 t wdd2 t wdh1 a3 a0 t ad t rwh t rwh t rdh1 t rwh t rdh1 figure 17.47 pseudo-sram bus cycle (static column mode, rcd = 0, a3w = 1, tpc = 0)
478 ckio a25 a4 rd/ wr oe / rfsh (read) ce wen (write) d31 d0 (read) d31 d0 (write) bs t r t rw t c1 t c1w t c2 t c1 t c1w t c2 (t pc )(t pc ) t bsd t bsd t bsd t bsd t ad t as a3 a0 t ad t rwd t rws t rds1 t oed t oed t oed t wed t wed t wds t wdh3 t wdh3 t wed t rdh1 t rds1 t ced t rwh t ah t rwh t rwh t ah t ah t oed t wed t ced t rwd t ad t as t wdd2 t wdd2 t wdh1 t rdh1 figure 17.48 pseudo-sram bus cycle (static column mode, rcd = 1, a3w = 2, tpc = 1)
479 ckio (high) oe / rfsh ce t rc t rr1 t rr2 (t pc ) t oed t oed figure 17.49 pseudo-sram auto-refresh cycle (tras = 1, tpc = 1) ckio oe / rfsh ce t rc t rr1 t rrw t rrw t rr2 (t pc )(t pc ) t oed t oed (high) figure 17.50 pseudo-sram auto-refresh cycle (tras = 2, tpc = 1) ckio (high) oe / rfsh ce t rc t rr1 t sr t sr2 (t pc )(t pc ) t oed t oed figure 17.51 pseudo-sram self-refresh cycle (tpc = 0)
480 17.3.9 pcmcia timing t pcm1 t pcm2 ckio a25 a0 cexx rd/ wr rd (read) d15 d0 (read) we1 (write) d15 d0 (write) bs t ad t ad t csd1 t csd1 t rwd t rsd t rsd t rwd t wed t wdd1 t wed t rds1 t rdh1 t bsd t bsd t wdh4 t wdh1 figure 17.52 pcmcia memory bus cycle (ted = 0, teh = 0, no wait)
481 ckio t pcm0 t pcm0w t pcm1 t pcm1w t pcm1w t pcm2 t pcm2w a25 a0 cexx rd/ wr rd (read) d15 d0 (read) we1 (write) d15 d0 (write) bs wait t ad t csd1 t rwd t ad t csd1 t rwd t wdh4 t rsd t rsd t wed t wdd1 t wed1 t wdh1 t rdh1 t bsd t wts t wth t wts t wth t rds1 t bsd figure 17.53 pcmcia memory bus cycle (ted = 2, teh = 1, 1 wait, external wait)
482 ckio t pcm1 t pcm2 t pcm1 t pcm2 t pcm1 t pcm2 t pcm1 t pcm2 a25 a4 a3 a0 cexx rd/ wr rd (read) d15 d0 (read) bs t ad t ad t csd1 t rwd t csd1 t rwd t ad t ad t ad t ad t rsd t rsd t rdh1 t rdh1 t rsd t rsd t bsd t bsd t bsd t bsd t rds1 t rds1 note: even though burst mode is set, write cycle operation is the same as in normal mode. figure 17.54 pcmcia memory bus cycle (burst read, ted = 0, teh = 0, no wait)
483 ckio t pcm0 t pcm1 t pcm1w t pcm1w t pcm1w t pcm2 t pcm1 t pcm1w t pcm2 t pcm2w a25 a4 a3 a0 cexx rd/ wr rd (read) d15 d0 (read) bs wait t ad t ad t csd1 t rwd t csd1 t rwd t ad t ad t ad t rsd t rsd t rsd t rsd t bsd t bsd t bsd t bsd t rds1 t rdh1 t rdh1 t rds1 t wts t wth t wts t wts t wth t wth note: even though burst mode is set, the write cycle operation is the same as in normal mode. figure 17.55 pcmcia memory bus cycle (burst read, ted = 1, teh = 1, 2 waits, burst pitch = 3)
484 t pci1 t pci2 ckio a25 a0 cexx rd/ wr iciord (read) d15 d0 (read) iciowr (write) d15 d0 (write) bs t ad t ad t csd1 t csd1 t rwd t icrsd t icrsd t rwd t icwsd t wdd1 t icwsd t rdh1 t rds1 t bsd t bsd t wdh1 t wdh4 figure 17.56 pcmcia i/o bus cycle (ted = 0, teh = 0, no wait)
485 ckio t pci0 t pci0w t pci1 t pci1w t pci1w t pci2 t pci2w a25 a0 cexx rd/ wr iciord (read) d15 d0 (read) iciowr (write) d15 d0 (write) bs wait iois16 t ad t csd1 t rwd t ad t csd1 t rwd t icrsd t icrsd t icwsd t wdd1 t icwsd t wdh1 t wdh4 t rdh1 t bsd t bsd t wts t wth t wts t wth t io16s t io16h t rds1 figure 17.57 pcmcia i/o bus cycle (ted = 2, teh = 1, 1 wait, external wait)
486 ckio t pci0 t pci1 t pci1w t pci2 t pci1 t pci1w t pci2 t pci2w a25 a4 a0 cexx rd/ wr iciord (read) d15 d0 (read) iciowr (write) d15 d0 (write) bs wait iois16 t ad t ad t csd1 t csd1 t rwd t rwd t wdd1 t wdh3 t wdh4 t bsd t bsd t ad t ad t icrsd t icrsd t icrsd t icrsd t icwsd t wts t wth t wth t io16s t io16h t ad t rds1 t csd1 t rds1 t icwsd t icwsd t icwsd t rdh1 t rdh1 t wdd2 t wdh1 t bsd t bsd t wts figure 17.58 pcmcia i/o bus cycle (ted = 1, teh = 1, 1 wait, bus sizing)
487 17.3.10 peripheral module signal timing table 17.9 peripheral module signal timing (conditions: v cc = 3.15?.6 v, t a = ?0 to + 75?) ?0 module item symbol min max unit figure tmu, timer input setup time t clks1 12 ns 17.59 rtc timer clock input setup time t cks 12 ns 17.60 timer clock single edge t tckwh 1.5 tcyc 17.60 pulse width both edges t tckwl 2.5 tcyc 17.60 oscillation settling time t rosc 3 s 17.61 sci input clock cycle asynchronous t scyc 4 tcyc 17.62, 17.63 synchronous 6 tcyc 17.62, 17.63 input clock rise time t sckr 1.5 tcyc 17.62 input clock fall time t sckf 1.5 tcyc 17.62 input clock pulse width t sckw 0.4 0.6 tscyc 17.62 transmit data delay time t txd 100 ns 17.63 receive data setup time (synchronous) t rxs 100 ns 17.63 receive data hold time (synchronous) t rxh 100 ns 17.63 port output data delay time t portd 15 ns 17.64 input data setup time t ports 12 ns 17.64 input data hold time t porth 5 ns 17.64
488 t tclks ckio tclk (input) figure 17.59 tclk input timing t tcks t tcks t tckwh t tckwl ckio tclk (input) figure 17.60 tclk clock input timing rtc crystal oscillator stable oscillation v cc v ccmin t rosc figure 17.61 rtc crystal oscillator power-on oscillation settling time t sckw t sckr t sckf t scyc sck figure 17.62 sck input clock timing
489 t scyc t txd sck txd (data trans- mission) rxd (data reception) t rxh t rxs figure 17.63 synchronous mode sci input/output timing t ports port 7 port 0 (read) port 7 port 0 (write) t porth t portd figure 17.64 i/o port input/output timing
490 17.3.11 ac characteristics test conditions ? input/output signal reference level: 1.5 v (v cc = 3.3?.6 v). ? input pulse level: v ss to 3.0 v (when reset , breq , nmi, irl3 irl0 , ckio, md5?d0 are v ss to v cc ). ? input rise/fall time: 1 ns i ol i oh c l v ref lsi output pin dut output notes: 1. 2. c l is the total capacitance including the test jig probe, as shown below: 30 pf: ckio, ras , casxx , cs0 cs6 , ce2a , ce2b , back 50 pf: all other pins i ol and i oh are the values shown in table 17.3 figure 17.65 output load circuit
491 appendix a pin functions a.1 pin states table a.1 shows pin states during resets, power-down states, and the bus-released state. table a.1 pin states during resets, power-down states, and bus-released state bus- power-on manual power-down state released category pin reset reset standby sleep state clock ckio io *1 io *1 io *1 io *1 io *1 extal i *1 i *1 i *1 i *1 i *1 xtal o *1 o *1 o *1 o *1 o *1 extal2 iiiii xtal2 ooooo system control reset iiiii breq iiiii back ooool ca iiiii status0, status1 ooooo md0/sck iiiio *2 io *2 md1/txd iiiio *3 io *3 md2/rxd iiiii md3/ ce2a iih *4 izh *5 ih *4 iz *4 md4/ ce2b iih *4 izh *5 ih *4 iz *4 md5/ ras2 iio *6 izo *7 io *6 izo *7 interrupt nmi iiiii irl3 to irl0 iiiii irqout ooooo
492 table a.1 pin states during resets, power-down states, and bus-released state (cont) bus- power-on manual power-down state released category pin reset reset standby sleep state address bus a25 to a0 o o z o z data bus d31 to d30 z zo *8 zo *8 zo *8 zo *8 d29 to d24 zzzzz d23 to d16/ port7 to port0 zzk *10 zk *10 zk *10 zk *10 d15 to d0 z i z i z bus control cs0 to cs4 hozh *11 hz cs5 / ce1a hozh *11 hz cs6 / ce1b hozh *11 hz bs hozh *11 hz ras / ce hozo *12 ozo *12 casll / cas / oe hozo *12 ozo *12 caslh hozo *12 ozo *12 cashl / cas2l hozo *12 ozo *12 cashh / cas2h hozo *12 ozo *12 dqmll/ we0 hozh *11 hz dqmlu/ we1 hozh *11 hz dqmul/ we2 / iciord hozh *11 hz dqmuu/ we3 / iciowr hozh *11 hz rd/ wr hoz hz rd hoz hz cke hoooo wait zi zi z iois16 zi zi z tmu/rtc tclk z i io *13 io *14 io *14 pll cap1, cap2 io io io io io i: input o: output h: high-level output
493 l: low-level output z: high impedance k: input pin is high impedance, output pin holds its state notes: 1. dependent on the clock mode (md2?d0 setting). 2. when sci and port are not used, i. when used, i or o depending on register setting. 3. when sci and port are not used, i. when used, o. 4. when pcmcia is not used, i. when used, h or z. 5. when pcmcia is not used, i. when used, z or h depending on register setting. 6. when area 2 dram is not used, i. when used, o. 7. when area 2 dram is not used, i. when used, z or o depending on register setting. 8. o when the port function is used. 9. z when the port function is used. 10. when the port function is used, k depending on register setting. 11. z or h depending on register setting. 12. z or o depending on register setting. 13. in standby mode, i or o depending on register setting. in hardware standby mode, i or l depending on register setting. 14. i or o depending on register setting.
494 a.2 pin specifications table a.2 shows the pin specifications. table a.2 pin specifications pin pin no. i/o function md5/ ras2 130 i/o operating mode pin (endian switching)/ ras (for dram). md signal is fetched in at power-on reset. switched to ras on area 2 dram enabling by register. md4/ ce2b 103 i/o operating mode pin (area 0 bus width)/pcmcia ce pin. md signal is fetched in at power-on reset. switched to ce2b on area 6 pcmcia enabling by register. md3/ ce2a 104 i/o operating mode pin (area 0 bus width)/pcmcia ce pin. md signal is fetched in at power-on reset. switched to ce2a on area 5 pcmcia enabling by register. md2/rxd 84 i operating mode pin/serial data input. md signal is fetched in at power-on reset. switched to rxd on sci enabling by register. md1/txd 85 i/o operating mode pin/serial data output. md signal is fetched in at power-on reset. switched to txd on sci enabling by register. md0/sck 86 i/o operating mode pin/serial clock. md signal is fetched in at power-on reset. switched to sck on sci enabling by register. status1 97 o processor status status0 98 o processor status a25 to a0 72 to 70, 67 to 61, 58 to 56, 53 to 51, 48 to 43, 40 to 37 o address bus d31 to d24 140 to 143, 1 to 4 i/o data bus d23 to d16/ port 7 to port 0 5, 8 to 14 i/o data bus / i/o port
495 table a.2 pin specifications (cont) pin pin no. i/o function d15 to d0 15 to 16, 21 to 29, 32 to 36 i/o data bus cs6 / ce1b 108 o chip select 6/pcmcia ce cs5 / ce1a 109 o chip select 5/pcmcia ce cs4 to cs0 110 to 114 o chip select 4?hip select 0 bs 105 o bus cycle start ras / ce 129 o dram, synchronous dram ras /pseudo-sram ce cashh / cas2h 119 o d31?24 (dram cas )/d15?8 (area 2 dram cas ) select signal cashl / cas2l 120 o d23-d16 (dram cas )/d7?0 (area 2 dram cas ) select signal caslh 125 o d15?8 select signal (dram cas ) casll / cas / oe 126 o d7?0 select (dram cas )/memory select signal (synchronous dram cas /pseudo-sram oe ) we3 /dqmuu/ iciowr 117 o d31?24 select signal (normal memory, pseudo-sram we /synchronous dram dqm)/io write (pcmcia, pcmcib) we2/dqmul/ iciord 118 o d23?16 select signal (normal memory, pseudo-sram we /synchronous dram dqm)/io write (pcmcia, pcmcib) we1 /dqmlu 123 o d15?8 select signal (normal memory, pseudo-sram we/synchronous dram dqm) we0 /dqmll 124 o d7?0 select signal (normal memory, pseudo-sram we/synchronous dram dqm) rd/ wr 106 o read/write (synchronous dram/dram/pcmcia) rd 107 o read pulse (pcmcia/normal memory) wait 132 i hardware wait request iois16 94 i io16 bit indication (pcmcia io area) breq 87 i bus request back 96 o bus acknowledge irqout 95 o interrupt request notification reset 88 i reset ca 81 i chip active causes a transition to hardware standby mode when low. drive high in a power-on reset.
496 table a.2 pin specifications (cont) pin pin no. i/o function nmi 89 i nonmaskable interrupt request irl3 to irl0 90 to 93 i external interrupt source input tclk 134 i/o timer external clock input/rtc clock output extal 79 i external clock/crystal resonator pin xtal 80 o crystal resonator pin cap1 74 o external capacitance pin (for pll1) cap2 77 o external capacitance pin (for pll2) ckio 101 i/o system clock input/output cke 131 o clock enable control (for synchronous dram) xtal2 136 o crystal resonator pin (for on-chip rtc) extal2 137 i crystal resonator pin (for on-chip rtc) nc 99 o leave unconnected v cc 7, 18, 20, 31, 42, 50, 55, 60, 69, 81, 83, 102, 116, 122, 128, 139 power supply power supply (3.3 v) v cc (rtc) 135 power supply rtc oscillator power supply (3.3 v) v cc (pll) 75, 78 power supply pll power supply (3.3 v) v ss 6, 17, 19, 30, 41, 49, 54, 59, 68, 82, 100, 115, 121, 127, 133, 144 power supply power supply (0 v) v ss (rtc) 138 power supply rtc oscillator power supply (0 v) v ss (pll) 73, 76 power supply pll power supply (0 v) note: except in hardware standby mode, power must be supplied constantly to all power supply pins. in hardware standby mode, power should be supplied at least to the rtc power supply pins.
497 a.3 handling of unused pins ? when rtc is not used ? extal2: pull up ? xtal2: leave unconnected ? v cc (rtc): power supply (3.3 v) ? v ss (rtc): power supply (0 v) ? when pll1 is not used ? cap1: leave unconnected ? v cc (pll): power supply (3.3 v) ? v ss (pll): power supply (0 v) ? when pll2 is not used ? cap2: leave unconnected ? v cc (pll): power supply (3.3 v) ? v ss (pll): power supply (0 v) ? when on-chip crystal oscillator is not used ? xtal: leave unconnected
498 a.4 pin states in access to each address space table a.3 pin states (normal memory/little-endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs0 enabled enabled enabled enabled rd r low low low low w high high high high rd / wr r high high high high w low low low low bs enabled enabled enabled enabled ras / ce high high high high cas / casll / oe high high high high caslh high high high high cashl / cas2l high high high high cashh / cas2h high high high high dqmll/ we0 r high high high high w low low high low dqmlu/ we1 r high high high high w high high low low dqmul/ we2 / iciord r high high high high w high high high high dqmuu/ we3 / iciowr r high high high high w high high high high md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data valid data invalid data valid data d15 to d8 high-z invalid data valid data valid data d23 to d16/ port7 to port0 high-z *5 high-z *5 high-z *5 high-z *5 d31 to d24 high-z *6 high-z *6 high-z *6 high-z *6
499 table a.3 pin states (normal memory/little-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r low low low low low low low w high high high high high high high rd / wr r high high high high high high high w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras / ce high high high high high high high cas / casll / oe high high high high high high high caslh high high high high high high high cashl / cas2l high high high high high high high cashh / cas2h high high high high high high high dqmll/ we0 r high high high high high high high w low high high high low high low dqmlu/ we1 r high high high high high high high w high low high high low high low dqmul/ we2 / iciord r high high high high high high high w high high low high high low low dqmuu/ we3 / iciowr r high high high high high high high w high high high low high low low md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data
500 table a.3 pin states (normal memory/little-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16/ port7 to port0 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr1.dramtp (2?) 101, high-z. 4. when wcr2 register wait setting is 0, disabled. 5. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register. 6. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
501 table a.4 pin states (normal memory/big-endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs0 enabled enabled high enabled rd r low low low low w high high high high rd / wr r high high high high w low low low low bs enabled enabled enabled enabled ras / ce high high high high cas / casll / oe high high high high caslh high high high high cashl / cas2l high high high high cashh / cas2h high high high high dqmll/ we0 r high high high high w low high low low dqmlu/ we1 r high high high high w high low high low dqmul/ we2 / iciord r high high high high w high high high high dqmuu/ we3 / iciowr r high high high high w high high high high md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data invalid data valid data valid data d15 to d8 high-z valid data invalid data valid data d23 to d16/ port7 to port0 high-z *5 high-z *5 high-z *5 high-z *5 d31 to d24 high-z *6 high-z *6 high-z *6 high-z *6
502 table a.4 pin states (normal memory/big-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r low low low low low low low w high high high high high high high rd / wr r high high high high high high high w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras / ce high high high high high high high cas / casll / oe high high high high high high high caslh high high high high high high high cashl / cas2l high high high high high high high cashh / cas2h high high high high high high high dqmll/ we0 r high high high high high high high w high high high low high low low dqmlu/ we1 r high high high high high high high w high high low high high low low dqmul/ we2 / iciord r high high high high high high high w high low high high low high low dqmuu/ we3 / iciowr r high high high high high high high w low high high high low high low md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 invalid data invalid data invalid data valid data invalid data valid data valid data
503 table a.4 pin states (normal memory/big-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16/ port7 to port0 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr1.dramtp (2?) 101, high-z. 4. when wcr2 register wait setting is 0, disabled. 5. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register . 6. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
504 table a.5 pin states (burst rom/little-endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs0 enabled enabled enabled enabled rd r low low low low w rd / wr r high high high high w bs enabled enabled enabled enabled ras / ce high high high high cas / casll / oe high high high high caslh high high high high cashl / cas2l high high high high cashh / cas2h high high high high dqmll/ we0 r high high high high w dqmlu/ we1 r high high high high w dqmul/ we2 / iciord r high high high high w dqmuu/ we3 / iciowr r high high high high w md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data valid data invalid data valid data d15 to d8 high-z invalid data valid data valid data d23 to d16/ port7 to port0 high-z *5 high-z *5 high-z *5 high-z *5 d31 to d24 high-z *6 high-z *6 high-z *6 high-z *6
505 table a.5 pin states (burst rom/little-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r low low low low low low low w rd / wr r high high high high high high high w bs enabled enabled enabled enabled enabled enabled enabled ras / ce high high high high high high high cas / casll / oe high high high high high high high caslh high high high high high high high cashl / cas2l high high high high high high high cashh / cas2h high high high high high high high dqmll/ we0 r high high high high high high high w dqmlu/ we1 r high high high high high high high w dqmul/ we2 / iciord r high high high high high high high w dqmuu/ we3 / iciowr r high high high high high high high w md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data
506 table a.5 pin states (burst rom/little-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16/ port7 to port0 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr1.dramtp (2?) 101, high-z. 4. when wcr2 register wait setting is 0, disabled. 5. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register. 6. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
507 table a.6 pin states (burst rom/big-endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs0 enabled enabled enabled enabled rd r low low low low w rd / wr r high high high high w bs enabled enabled enabled enabled ras / ce high high high high cas / casll / oe high high high high caslh high high high high cashl / cas2l high high high high cashh / cas2h high high high high dqmll/ we0 r high high high high w dqmlu/ we1 r high high high high w dqmul/ we2 / iciord r high high high high w dqmuu/ we3 / iciowr r high high high high w md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data invalid data valid data valid data d15 to d8 high-z valid data invalid data valid data d23 to d16/ port7 to port0 high-z *5 high-z *5 high-z *5 high-z *5 d31 to d24 high-z *6 high-z *6 high-z *6 high-z *6
508 table a.6 pin states (burst rom/big-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r low low low low low low low w rd / wr r high high high high high high high w bs enabled enabled enabled enabled enabled enabled enabled ras / ce high high high high high high high cas / casll / oe high high high high high high high caslh high high high high high high high cashl / cas2l high high high high high high high cashh / cas2h high high high high high high high dqmll/ we0 r high high high high high high high w dqmlu/ we1 r high high high high high high high w dqmul/ we2 / iciord r high high high high high high high w dqmuu/ we3 / iciowr r high high high high high high high w md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 invalid data invalid data invalid data valid data invalid data valid data valid data
509 table a.6 pin states (burst rom/big-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16/ port7 to port0 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr1.dramtp (2?) 101, high-z. 4. when wcr2 register wait setting is 0, disabled. 5. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register . 6. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
510 table a.7 pin states (dram/little-endian) 16-bit bus width (area 3) 16-bit bus width (area 2) pin byte access (address 2n) byte access (address 2n + 1) word/ longword access byte access (address 2n) byte access (address 2n + 1) word/ longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled rd r high high high high high high w high high high high high high rd / wr r high high high high high high w low low low low low low bs enabled enabled enabled enabled enabled enabled ras / ce low low low high high high cas / casll / oe low high low high high high caslh high low low high high high cashl / cas2l high high high low high low cashh / cas2h high high high high low low dqmll/ we0 r high high high high high high w high high high high high high dqmlu/ we1 r high high high high high high w high high high high high high dqmul/ we2 / iciord r high high high high high high w high high high high high high dqmuu/ we3 / iciowr r high high high high high high w high high high high high high md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 low low low cke disabled disabled disabled disabled disabled disabled wait disabled disabled disabled disabled disabled disabled iois16 disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address d7 to d0 valid data invalid data valid data valid data invalid data valid data d15 to d8 invalid data valid data valid data invalid data valid data valid data
511 table a.7 pin states (dram/little-endian) (cont) 16-bit bus width (area 3) 16-bit bus width (area 2) pin byte access (address 2n) byte access (address 2n + 1) word/ longword access byte access (address 2n) byte access (address 2n + 1) word/ longword access d23 to d16/ port7 to port0 high-z *4 high-z *4 high-z *4 high-z *4 high-z *4 high-z *4 d31 to d24 high-z *5 high-z *5 high-z *5 high-z *5 high-z *5 high-z *5
512 table a.7 pin states (dram/little-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r high high high high high high high w high high high high high high high rd / wr r high high high high high high high w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras / ce low low low low low low low cas / casll / oe low high high high low high low caslh high low high high low high low cashl / cas2l high high low high high low low cashh / cas2h high high high low high low low dqmll/ we0 r high high high high high high high w high high high high high high high dqmlu/ we1 r high high high high high high high w high high high high high high high dqmul/ we2 / iciord r high high high high high high high w high high high high high high high dqmuu/ we3 / iciowr r high high high high high high high w high high high high high high high md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z high-z high-z high-z high-z high-z high-z cke disabled disabled disabled disabled disabled disabled disabled wait disabled disabled disabled disabled disabled disabled disabled iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data
513 table a.7 pin states (dram/little-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16/ port7 to port0 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr1.dramtp (2?) 101, high-z. 4. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register. 5. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
514 table a.8 pin states (dram/big-endian) 16-bit bus width (area 3) 16-bit bus width (area 2) pin byte access (address 2n) byte access (address 2n + 1) word/ longword access byte access (address 2n) byte access (address 2n + 1) word/ longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled rd r high high high high high high w high high high high high high rd / wr r high high high high high high w low low low low low low bs enabled enabled enabled enabled enabled enabled ras / ce low low low high high high cas / casll / oe high low low high high high caslh low high low high high high cashl / cas2l high high high high low low cashh / cas2h high high high low high low dqmll/ we0 r high high high high high high w high high high high high high dqmlu/ we1 r high high high high high high w high high high high high high dqmul/ we2 / iciord r high high high high high high w high high high high high high dqmuu/ we3 / iciowr r high high high high high high w high high high high high high md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 low low low cke disabled disabled disabled disabled disabled disabled wait disabled disabled disabled disabled disabled disabled iois16 disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address d7 to d0 invalid data valid data valid data invalid data valid data valid data d15 to d8 valid data invalid data valid data valid data invalid data valid data
515 table a.8 pin states (dram/big-endian) (cont) 16-bit bus width (area 3) 16-bit bus width (area 2) pin byte access (address 2n) byte access (address 2n + 1) word/ longword access byte access (address 2n) byte access (address 2n + 1) word/ longword access d23 to d16/ port7 to port0 high-z *4 high-z *4 high-z *4 high-z *4 high-z *4 high-z *4 d31 to d24 high-z *5 high-z *5 high-z *5 high-z *5 high-z *5 high-z *5
516 table a.8 pin states (dram/big-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r high high high high high high high w high high high high high high high rd / wr r high high high high high high high w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras / ce low low low low low low low cas / casll / oe high high high low high low low caslh high high low high high low low cashl / cas2l high low high high low high low cashh / cas2h low high high high low high low dqmll/ we0 r high high high high high high high w high high high high high high high dqmlu/ we1 r high high high high high high high w high high high high high high high dqmul/ we2 / iciord r high high high high high high high w high high high high high high high dqmuu/ we3 / iciowr r high high high high high high high w high high high high high high high md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z high-z high-z high-z high-z high-z high-z cke disabled disabled disabled disabled disabled disabled disabled wait disabled disabled disabled disabled disabled disabled disabled iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 invalid data invalid data invalid data valid data invalid data valid data valid data
517 table a.8 pin states (dram/big-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16/ port7 to port0 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr1.dramtp (2?) 101, high-z. 4. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register. 5. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
518 table a.9 pin states (synchronous dram/little-endian) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r high high high high high high high w high high high high high high high rd / wr r high high high high high high high w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras / ce low low low low low low low cas / casll / oe low low low low low low low caslh high high high high high high high cashl / cas2l high high high high high high high cashh / cas2h high high high high high high high dqmll/ we0 r low high high high low high low w low high high high low high low dqmlu/ we1 r high low high high low high low w high low high high low high low dqmul/ we2 / iciord r high high low high high low low w high high low high high low low dqmuu/ we3 / iciowr r high high high low high low low w high high high low high low low md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z high-z high-z high-z high-z high-z high-z cke high *3 high *3 high *3 high *3 high *3 high *3 high *3 wait disabled disabled disabled disabled disabled disabled disabled iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address, command address, command address, command address, command address, command address, command address, command d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data
519 table a.9 pin states (synchronous dram/little-endian) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16/ port7 to port0 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. normally high. low in self-refreshing.
520 table a.10 pin states (synchronous dram/big-endian) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r high high high high high high high w high high high high high high high rd / wr r high high high high high high high w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras / ce low low low low low low low cas / casll / oe low low low low low low low caslh high high high high high high high cashl / cas2l high high high high high high high cashh / cas2h high high high high high high high dqmll/ we0 r high high high low high low low w low high high low high low low dqmlu/ we1 r high high low high high low low w high high low high high low low dqmul/ we2 / iciord r high low high high low high low w high low low high low high low dqmuu/ we3 / iciowr r low high high high low high low w low high high low low high low md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z high-z high-z high-z high-z high-z high-z cke high *3 high *3 high *3 high *3 high *3 high *3 high *3 wait disabled disabled disabled disabled disabled disabled disabled iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address, command address, command address, command address, command address, command address, command address, command d7 to d0 invalid data invalid data invalid data valid data invalid data valid data valid data
521 table a.10 pin states (synchronous dram/big-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16/ port7 to port0 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. normally high. low in self-refreshing.
522 table a.11 pin states (pseudo-sram/little-endian) 16-bit bus width pin byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs0 enabled enabled enabled rd r high high high w high high high rd / wr r high high high w low low low bs enabled enabled enabled ras / ce low low low cas / casll / oe low low low caslh high high high cashl / cas2l high high high cashh / cas2h high high high dqmll/ we0 r high high high w low high low dqmlu/ we1 r high high high w high low low dqmul/ we2 / iciord r high high high w high high high dqmuu/ we3 / iciowr r high high high w high high high md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z high-z high-z cke disabled disabled disabled wait disabled disabled disabled iois16 disabled disabled disabled a25 to a0 address address address d7 to d0 valid data invalid data valid data d15 to d8 invalid data valid data valid data d23 to d16/ port7 to port0 high-z *3 high-z *3 high-z *3 d31 to d24 high-z *4 high-z *4 high-z *4
523 table a.11 pin states (pseudo-sram/little-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r high high high high high high high w high high high high high high high rd / wr r high high high high high high high w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras / ce low low low low low low low cas / casll / oe low low low low low low low caslh high high high high high high high cashl / cas2l high high high high high high high cashh / cas2h high high high high high high high dqmll/ we0 r high high high high high high high w low high high high low high low dqmlu/ we1 r high high high high high high high w high low high high low high low dqmul/ we2 / iciord r high high high high high high high w high high low high high low low dqmuu/ we3 / iciowr r high high high high high high high w high high high low high low low md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z high-z high-z high-z high-z high-z high-z cke disabled disabled disabled disabled disabled disabled disabled wait disabled disabled disabled disabled disabled disabled disabled iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data
524 table a.11 pin states (pseudo-sram/little-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16/ port7 to port0 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register. 4. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
525 table a.12 pin states (pseudo-sram/big-endian) 16-bit bus width pin byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs0 enabled enabled enabled rd r high high high w high high high rd / wr r high high high w low low low bs enabled enabled enabled ras / ce low low low cas / casll / oe low low low caslh high high high cashl / cas2l high high high cashh / cas2h high high high dqmll/ we0 r high high high w high low low dqmlu/ we1 r high high high w low high low dqmul/ we2 / iciord r high high high w high high high dqmuu/ we3 / iciowr r high high high w high high high md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z high-z high-z cke disabled disabled disabled wait disabled disabled disabled iois16 disabled disabled disabled a25 to a0 address address address d7 to d0 invalid data valid data valid data d15 to d8 valid data invalid data valid data d23 to d16/ port7 to port0 high-z *3 high-z *3 high-z *3 d31 to d24 high-z *4 high-z *4 high-z *4
526 table a.12 pin states (pseudo-sram/big-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access cs6 to cs0 enabled enabled enabled enabled enabled enabled enabled rd r high high high high high high high w high high high high high high high rd / wr r high high high high high high high w low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled ras / ce low low low low low low low cas / casll / oe low low low low low low low caslh high high high high high high high cashl / cas2l high high high high high high high cashh / cas2h high high high high high high high dqmll/ we0 r high high high high high high high w high high high low high low low dqmlu/ we1 r high high high high high high high w high high low high high low low dqmul/ we2 / iciord r high high high high high high high w high low high high low high low dqmuu/ we3 / iciowr r high high high high high high high w low high high high low high low md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z high-z high-z high-z high-z high-z high-z cke disabled disabled disabled disabled disabled disabled disabled wait disabled disabled disabled disabled disabled disabled disabled iois16 disabled disabled disabled disabled disabled disabled disabled a25 to a0 address address address address address address address d7 to d0 invalid data invalid data invalid data valid data invalid data valid data valid data
527 table a.12 pin states (pseudo-sram/big-endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n + 1) byte access (address 4n + 2) byte access (address 4n + 3) word access (address 4n) word access (address 4n + 2) longword access d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16/ port7 to port0 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register. 4. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
528 table a.13 pin states (pcmcia/little-endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs0 enabled enabled high enabled rd r low low low low w high high high high rd / wr r high high high high w low low low low bs enabled enabled enabled enabled ras / ce high high high high cas / casll / oe high high high high caslh high high high high cashl / cas2l high high high high cashh / cas2h high high high high dqmll/ we0 r high high high high w high high high high dqmlu/ we1 r high high high high w low low low low dqmul/ we2 / iciord r high high high high w high high high high dqmuu/ we3 / iciowr r high high high high w high high high high md3/ ce2a high high low low md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data valid data invalid data valid data d15 to d8 high-z invalid data valid data valid data d23 to d16/ port7 to port0 high-z *5 high-z *5 high-z *5 high-z *5 d31 to d24 high-z *6 high-z *6 high-z *6 high-z *6
529 table a.13 pin states (pcmcia/little-endian) (cont) pcmcia memory interface (area 6) pcmcia/io interface (area 6) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access cs6 to cs0 enabled enabled high enabled enabled enabled high enabled rd r low low low low high high high high w high high high high high high high high rd / wr r high high high high high high high high w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras / ce high high high high high high high high cas / casll / oe high high high high high high high high caslh high high high high high high high high cashl / cas2l high high high high high high high high cashh / cas2h high high high high high high high high dqmll/ we0 r high high high high high high high high w high high high high high high high high dqmlu/ we1 r high high high high high high high high w low low low low high high high high dqmul/ we2 / iciord r high high high high low low low low w high high high high high high high high dqmuu/ we3 / iciowr r high high high high high high high high w high high high high low low low low md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high high low low high high low low md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled disabled disabled disabled *5 disabled *5 a25 to a0 address address address address address address address address
530 table a.13 pin states (pcmcia/little-endian) (cont) pcmcia memory interface (area 6) pcmcia/io interface (area 6) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access d7 to d0 valid data valid data invalid data valid data valid data valid data invalid data valid data d15 to d8 high-z invalid data valid data valid data high-z invalid data valid data valid data d23 to d16/ port7 to port0 high-z *6 high-z *6 high-z *6 high-z *6 high-z *6 high-z *6 high-z *6 high-z *6 d31 to d24 high-z *7 high-z *7 high-z *7 high-z *7 high-z *7 high-z *7 high-z *7 high-z *7 notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr1.dramtp (2?) 101, high-z. 4. when wcr2 register wait setting is 0, disabled. 5. drive high. 6. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register. 7. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
531 table a.14 pin states (pcmcia/big-endian) 8-bit bus width 16-bit bus width pin byte/word/long- word access byte access (address 2n) byte access (address 2n + 1) word/longword access cs6 to cs0 enabled enabled high enabled rd r low low low low w high high high high rd / wr r high high high high w low low low low bs enabled enabled enabled enabled ras / ce high high high high cas / casll / oe high high high high caslh high high high high cashl / cas2l high high high high cashh / cas2h high high high high dqmll/ we0 r high high high high w high high high high dqmlu/ we1 r high high high high w low low low low dqmul/ we2 / iciord r high high high high w high high high high dqmuu/ we3 / iciowr r high high high high w high high high high md3/ ce2a high high low low md4/ ce2b high-z or high *2 high-z or high *2 high-z or high *2 high-z or high *2 md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled a25 to a0 address address address address d7 to d0 valid data invalid data valid data valid data d15 to d8 high-z valid data invalid data valid data d23 to d16/ port7 to port0 high-z *5 high-z *5 high-z *5 high-z *5 d31 to d24 high-z *6 high-z *6 high-z *6 high-z *6
532 table a.14 pin states (pcmcia/big-endian) (cont) pcmcia memory interface (area 6) pcmcia/io interface (area 6) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access cs6 to cs0 enabled enabled high enabled enabled enabled high enabled rd r low low low low high high high high w high high high high high high high high rd / wr r high high high high high high high high w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras / ce high high high high high high high high cas / casll / oe high high high high high high high high caslh high high high high high high high high cashl / cas2l high high high high high high high high cashh / cas2h high high high high high high high high dqmll/ we0 r high high high high high high high high w high high high high high high high high dqmlu/ we1 r high high high high high high high high w low low low low high high high high dqmul/ we2 / iciord r high high high high low low low low w high high high high high high high high dqmuu/ we3 / iciowr r high high high high high high high high w high high high high low low low low md3/ ce2a high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 high-z or high *1 md4/ ce2b high high low low high high low low md5/ ras2 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 high-z or high *3 cke disabled disabled disabled disabled disabled disabled disabled disabled wait enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 enabled *4 iois16 disabled disabled disabled disabled disabled disabled enabled enabled a25 to a0 address address address address address address address address
533 table a.14 pin states (pcmcia/big-endian) (cont) pcmcia memory interface (area 6) pcmcia/io interface (area 6) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access byte/ word/ long- word access byte access (ad- dress 2n) byte access (ad- dress 2n + 1) word/ long- word access d7 to d0 valid data invalid data valid data valid data valid data invalid data valid data valid data d15 to d8 high-z valid data invalid data valid data high-z valid data invalid data valid data d23 to d16/ port7 to port0 high-z *5 high-z *5 high-z *5 high-z *5 high-z *5 high-z *5 high-z *5 high-z *5 d31 to d24 high-z *6 high-z *6 high-z *6 high-z *6 high-z *6 high-z *6 high-z *6 high-z *6 notes: 1. when bcr1.a5pcm = 0, high-z. 2. when bcr1.a6pcm = 0, high-z. 3. when bcr1.dramtp (2?) 101, high-z. 4. when wcr2 register wait setting is 0, disabled. 5. when bcr2.porten = 0, high-z. when bcr2.porten = 1, dependent on pctr register. 6. when bcr2.porten = 0, high-z. when bcr2.porten = 1, d31 and d30 only data output.
534 appendix b control registers b.1 register address map the address map of memory-mapped control registers is shown in table b-1. the following module abbreviations are used. mmu: memory management unit ubc: user break controller cpg: clock pulse generator bsc: bus state controller rtc: realtime clock intc: interrupt controller tmu: timer unit sci: serial communication interface cac: cache the bus column shows the internal bus to which the control register is connected. s: system bus, to which the cpu, cache, tlb, multiplier, and ubc are connected. c: cache bus, to which the bsc and cache are connected. p: peripheral bus, to which the bsc and peripheral modules (rtc, intc, tmu, and sci) are connected. the size column shows the register size in bits. the access size column shows the size used when the control register is accessed (read or written). if a size other than that indicated is used in an access, the result will be incorrect.
535 table b.1 memory-mapped control register address map register abbreviation module bus address size access size page table entry high register pteh mmu s h'fffffff0 32 32 page table entry low register ptel mmu s h'fffffff4 32 32 translation table page register ttb mmu s h'fffffff8 32 32 tlb exception address register tea mmu s h'fffffffc 32 32 mmu control register mmucr mmu s h'ffffffe0 32 32 break asid register a basra ubc s h'ffffffe4 8 8 break asid register b basrb ubc s h'ffffffe8 8 8 cache control register ccr cac s h'ffffffec 32 32 trapa exception register tra intc s h'ffffffd0 32 32 exception event register expevt intc s h'ffffffd4 32 32 interrupt event register intevt intc s h'ffffffd8 32 32 break address register a bara ubc s h'ffffffb0 32 32 break address mask register a bamra ubc s h'ffffffb4 8 8 break bus cycle register a bbra ubc s h'ffffffb8 16 16 break address register b barb ubc s h'ffffffa0 32 32 break address mask register b bamrb ubc s h'ffffffa4 8 8 break bus cycle register b bbrb ubc s h'ffffffa8 16 16 break data register b bdrb ubc s h'ffffff90 32 32 break data mask register b bdmrb ubc s h'ffffff94 32 32 break control register brcr ubc s h'ffffff98 16 16 frequency control register frqcr cpg s h'ffffff80 16 16 standby control register stbcr cpg s h'ffffff82 8 8 watchdog timer counter wtcnt cpg s h'ffffff84 8 r = 8, w = 16 watchdog timer control/status register wtcsr cpg s h'ffffff86 8 r = 8, w = 16 bus control register 1 bcr1 bsc c h'ffffff60 16 16 bus control register 2 bcr2 bsc c h'ffffff62 16 16
536 table b.1 memory-mapped control register address map (cont) register abbreviation module bus address size access size wait state control register 1 wcr1 bsc c h'ffffff64 16 16 wait state control register 2 wcr2 bsc c h'ffffff66 16 16 individual memory control register mcr bsc c h'ffffff68 16 16 dram control register dcr bsc c h'ffffff6a 16 16 pcmcia control register pcr bsc c h'ffffff6c 16 16 refresh timer control/status register rtcsr bsc c h'ffffff6e 16 16 refresh timer counter rtcnt bsc c h'ffffff70 16 16 refresh timer constant counter rtcor bsc c h'ffffff72 16 16 refresh count register rfcr bsc c h'ffffff74 16 16 port control register pctr bsc c h'ffffff76 16 16 port data register pdtr bsc c h'ffffff78 8 8 serial port register scsptr sci p h'ffffff7c 8 8 sdram mode register sdmr bsc c h'ffffd000 8 8 64 hz counter r64cnt rtc p h'fffffec0 8 8 second counter rseccnt rtc p h'fffffec2 8 8 minute counter rmincnt rtc p h'fffffec4 8 8 hour counter rhrcnt rtc p h'fffffec6 8 8 day-of-week counter rwkcnt rtc p h'fffffec8 8 8 day counter rdaycnt rtc p h'fffffeca 8 8 month counter rmoncnt rtc p h'fffffecc 8 8 year counter ryrcnt rtc p h'fffffece 8 8 second alarm register rsecar rtc p h'fffffed0 8 8 minute alarm register rminar rtc p h'fffffed2 8 8 hour alarm register rhrar rtc p h'fffffed4 8 8 day-of-week alarm register rwkar rtc p h'fffffed6 8 8 day alarm register rdayar rtc p h'fffffed8 8 8 month alarm register rmonar rtc p h'fffffeda 8 8 rtc control register 1 rcr1 rtc p h'fffffedc 8 8 rtc control register 2 rcr2 rtc p h'fffffede 8 8
537 table b.1 memory-mapped control register address map (cont) register abbreviation module bus address size access size interrupt control register icr intc p h'fffffee0 16 16 interrupt priority level setting register a ipra intc p h'fffffee2 16 16 interrupt priority level setting register b iprb intc p h'fffffee4 16 16 timer output control register tocr tmu p h'fffffe90 8 8 timer start register tstr tmu p h'fffffe92 8 8 timer constant register 0 tcor0 tmu p h'fffffe94 32 32 timer counter 0 tcnt0 tmu p h'fffffe98 32 32 timer control register 0 tcr0 tmu p h'fffffe9c 16 16 timer constant register 1 tcor1 tmu p h'fffffea0 32 32 timer counter 1 tcnt1 tmu p h'fffffea4 32 32 timer control register 1 tcr1 tmu p h'fffffea8 16 16 timer constant register 2 tcor2 tmu p h'fffffeac 32 32 timer counter 2 tcnt2 tmu p h'fffffeb0 32 32 timer control register 2 tcr2 tmu p h'fffffeb4 16 16 input capture register 2 tcpr2 tmu p h'fffffeb8 32 32 serial mode register scsmr sci p h'fffffe80 8 8 bit rate register scbrr sci p h'fffffe82 8 8 serial control register scscr sci p h'fffffe84 8 8 transmit data register sctdr sci p h'fffffe86 8 8 serial status register scssr sci p h'fffffe88 8 8 receive data register scrdr sci p h'fffffe8a 8 8 smartcard mode register scscmr sci p h'fffffe8c 8 8
538 b.2 register bit list a register bit list is shown in table b.2 table b.2 register bit list abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module sdmr bsc scsmr c/ a chr pe o/ e stop mp cks1 cks0 sci scbrr sci scscr tie rie te re mpie teie cke1 cke0 sci sctsr sci sctdr sci scssr tdre rdrf orer fer per tend mpb mpbt sci scrsr sci scrdr sci scscmr sdir sinv smif sci tocr tcoe tmu tstr str2 str1 str0 tmu tcor0 tmu tcnt0 tmu tcr0 ?nftmu unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tcor1 tmu tcnt1 tmu
539 table b.2 register bit list (cont) abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcr1 ?nftmu unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tcor2 tmu tcnt2 tmu tcr2 icpf unf tmu icpe1 icpe0 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tcpr2 tmu r64cnt 1hz 2hz 4hz 8hz 16hz 32hz 64hz rtc rseccnt 10 seconds 10 seconds 10 seconds 1 second 1 second 1 second 1 second rtc rmincnt 10 minutes 10 minutes 10 minutes 1 minute 1 minute 1 minute 1 minute rtc rhrcnt 10 hours 10 hours 1 hours 1 hour 1 hour 1 hour rtc rwkcnt day of week day of week day of week rtc rdaycnt 10 days 10 days 1 day 1 day 1 day 1 day rtc rmoncnt 10 months1 month 1 month 1 month 1 month rtc ryrcnt 10 years 10 years 10 years 10 years 1 year 1 year 1 year 1 year rtc rsecar enb 10 seconds 10 seconds 10 seconds 1 second 1 second 1 second 1 second rtc rminar enb 10 minutes 10 minutes 10 minutes 1 minute 1 minute 1 minute 1 minute rtc rhrar enb 10 hours 10 hours 1 hour 1 hour 1 hour 1 hour rtc rwkar enb day of week day of week day of week rtc rdayar enb 10 days 10 days 1 day 1 day 1 day 1 day rtc rmonar enb 10 months1 month 1 month 1 month 1 month rtc
540 table b.2 register bit list (cont) abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module rcr1 cf cie aie af rtc rcr2 pef pes2 pes1 pes0 rtcen adj reset start rtc icr nmil nmie intc ipra tmu0 tmu0 tmu0 tmu0 tmu1 tmu1 tmu1 tmu1 intc tmu2 tmu2 tmu2 tmu2 rtc rtc rtc rtc iprb wdt wdt wdt wdt ref ref ref ref intc scisciscisci bcr1 hizmem* hizcnt endian a0bst1 a0bst0 a5bst1 bsc a5bst0 a6bst1 a6bst0 dramtp2 dramtp1 dramtp0 a5pcm a6pcm bcr2 a6sz1 a6sz0 a5sz1 a5sz0 a4sz1 a4sz0 bsc a3sz1 a3sz0 a2sz1 a2sz0 a1sz1 a1sz0 porten wcr1 a6iw1 a6iw0 a5iw1 a5iw0 a4iw1 a4iw0 bsc a3iw1 a3iw0 a2iw1 a2iw0 a1iw1 a1iw0 a0iw1 a0iw0 wcr2 a6w2 a6w1 a6w0 a5w2 a5w1 a5w0 a4w2 a4w1 bsc a4w0 a3w1 a3w0 a1-2w1 a1-2w0 a0w2 a0w1 a0w0 mcr tpc1 tpc0 rcd1 rcd0 trwl1 trwl0 tras1 tras0 bsc be sz amx1 amx0 rfsh rmode edomode dcr tpc1 tpc0 rcd1 rcd0 tras1 tras0 bsc be amx1 amx0 rfsh rmode pcr bsc a5ted1 a5ted0 a6ted1 a6ted0 a5teh1 a5teh0 a6teh1 a6teh0 rtcsr bsc cmf cmie cks2 cks1 cks0 ovf ovie lmts rtcnt bsc rtcor bsc rfcr bsc pctr pb7pup pb7io pb6pup pb6io pb5pup pb5io pb4pup pb4io i/o pb3pup pb3io pb2pup pb2io pb1pup pb1io pb0pup pb0io pdtr pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt i/o scsptr spb1io spb1dt spb0io spb0dt i/o
541 table b.2 register bit list (cont) abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module frqcr stc2 ifc2 pfc2 ckoen cpg pllen pstby stc1 stc0 ifc1 ifc0 pfc1 pfc0 stbcr stby mstp2 mstp1 mstp0 power- down states wtcnt cpg wtcsr tme wt/ it rsts wovf iovf cks2 cks1 cks0 cpg bdrb bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 ubc bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 bdmrb bdm31 bdm30 bdm29 bdm28 bdm27 bdm26 bdm25 bdm24 ubc bdm23 bdm22 bdm21 bdm20 bdm19 bdm18 bdm17 bdm16 bdm15 bdm14 bdm13 bdm12 bdm11 bdm10 bdm9 bdm8 bdm7 bdm6 bdm5 bdm4 bdm3 bdm2 bdm1 bdm0 brcr cmfa cmfb pcba ubc dbeb pcbb seq barb bab31 bab30 bab29 bab28 bab27 bab26 bab25 bab24 ubc bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 bamrb basmb bamb1 bamb0 ubc bbrb ubc idb1 idb0 rwb1 rwb0 szb1 szb0 bara baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 ubc baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 bamra basma bama1 bama0 ubc bbra ubc ida1 ida0 rwa1 rwa0 sza1 sza0
542 table b.2 register bit list (cont) abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tra ccn expevt ccn intevt ccn mmucr ccn ?v rc rc tf ix at basra basa7 basa6 basa5 basa4 basa3 basa2 basa1 basa0 ubc basrb basb7 basb6 basb5 basb4 basb3 basb2 basb1 basb0 ubc ccr ccn ra 0 cf cb wt ce pteh ccn ptel ccn ? prprsz c d sh ttb ccn
543 table b.2 register bit list (cont) abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tea ccn legend sci: serial communication interface tmu: timer unit rtc: real time clock intc: interrupt controller bsc: bus state controller cpg: clock pulse generator ubc: user break controller ccn: cache controller unit
544 b.3 register states in reset and power-down states table b.3 register states in reset and power-down states reset states power-down states module register power-on manual standby sleep cpu r0?15 undefined undefined held held mach, macl undefined undefined held held pr undefined undefined held held pc h'a0000000 h'a0000000 held held sr initialized *1 initialized *1 held held ssr undefined undefined held held spc undefined undefined held held gbr undefined undefined held held vbr h'00000000 h'00000000 held held mmu pteh undefined undefined held held ptel undefined undefined held held ttb undefined undefined held held tea undefined undefined held held mmucr initialized* 2 initialized* 2 held held cache ccr h'00000000 h'00000000 held held intc icr h'8000/h'0000 *3 h'8000/h'0000 *3 held held ipra h'0000 h'0000 held held iprb h'0000 h'0000 held held tra undefined undefined held held expevt h'00000000 h'00000020 held held intevt undefined undefined held held ubc bara undefined held held held basra undefined held held held bamra undefined held held held
545 table b.3 register states in reset and power-down states (cont) reset states power-down states module register power-on manual standby sleep ubc bbra h'0000 h'0000 held held barb undefined held held held bamrb undefined held held held basrb undefined held held held bbrb h'0000 h'0000 held held bdmrb undefined held held held bdrb undefined held held held brcr h'0000 h'0000 held held cpg stbcr h'00 held held held frqcr h'0102 *4 held held held wtcnt h'00 *4 runs runs runs wtcsr h'00 *4 runs runs runs bsc bcr1 h'0000 held held held bcr2 h'3ffc held held held wcr1 h'3fff held held held wcr2 h'ffff held held held mcr h'0000 held held held dcr h'0000 held held held pcr h'0000 held held held rtcsr h'0000 runs held runs rtcnt h'0000 runs held runs rtcor h'0000 held held held rfcr h'0000 runs held runs pctr h'0000 held held held pdtr undefined held held held
546 table b.3 register states in reset and power-down states (cont) reset states power-down states module register power-on manual standby sleep tmu tocr h'00 h'00 held held tstr h'00 h'00 initialized/ held *5 held tcor0 h'ffffffff h'ffffffff held held tcnt0 h'ffffffff h'ffffffff held/runs *5 runs tcr0 h'0000 h'0000 held/runs *5 runs tcor1 h'ffffffff h'ffffffff held held tcnt1 h'ffffffff h'ffffffff held/runs *5 runs tcr1 h'0000 h'0000 held/runs *5 runs tcor2 h'ffffffff h'ffffffff held held tcnt2 h'ffffffff h'ffffffff held/runs *5 runs tcr2 h'0000 h'0000 held/runs *5 runs tcpr2 undefined undefined held held rtc r64cnt undefined runs runs runs rseccnt runs runs runs runs rmincnt runs runs runs runs rhrcnt runs runs runs runs rwkcnt runs runs runs runs rdaycnt runs runs runs runs rmoncnt runs runs runs runs ryrcnt runs runs runs runs rsecar held *6 held held held rminar held *6 held held held rhrar held *6 held held held rwkar held *6 held held held rdayar held *6 held held held rmonar held *6 held held held rcr1 h'00 initialized *7 held held rcr2 h'09 initialized *8 held held
547 table b.3 register states in reset and power-down states (cont) reset states power-down states module register power-on manual standby sleep sci scsmr h'00 h'00 h'00 h'00 *10 scbrr h'ff h'ff h'ff h'ff *10 scscr h'00 h'00 h'00 h'00 *10 sctdr h'ff h'ff h'ff h'ff *10 scssr h'84 h'84 h'84 h'84 *10 scrdr h'00 h'00 h'00 h'00 *10 scsptr initialized *9 held held held scscmr initialized *11 initialized *11 initialized *11 initialized *11 notes: 1. md = 1, rb = 1, bl = 1, i3?0 = b'1111 m, q, s, t are undefined. 2. the sv bit is undefined, other bits = 0. 3. h'8000: nmi pin is high / h'0000: nmi pin is low. 4. initialized in a power-on reset via the reset pin. held in a power-on reset via the wdt. 5. depends on the count clock mode. 6. only the enb bit is cleared. 7. cf bit is undefined, other bits = 0. 8. rtcen and start are held, other bits = 0. 9. bits 2 and 0 are undefined, other bits = 0 10. held when sci is operating, initialized when sci is not used. 11. bits 0, 2, and 3 are cleared, other bits are undefined.
548 appendix c load time variation due to load capacitance a graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated is connected to the sh7708r? pins. the graph shown in figure c.1 should be taken into consideration if the stipulated capacitance is exceeded in connecting an external device. +4.0 ns +3.0 ns +2.0 ns +1.0 ns +0.0 ns +0 pf +25 pf +50 pf load capacitance delay time figure c.1 load capacitance vs. delay time
549 appendix d list of models table d.1 list of models abbreviation voltage operating frequency mask version model marking package sh7718r 3.15 v to 3.6 v 100 mhz HD6417718Rf100 144-pin plastic a-mask HD6417718Rf100a lqfp (fp-144f)
550 appendix e package dimensions hitachi code jedec eiaj weight (reference value) fp-144f conforms 1.4 g unit: mm *dimension including the plating thickness base material dimension 0.08 0.10 0.5 20 22.0 0.2 108 73 109 72 37 144 1 36 22.0 0.2 1.0 0.5 0.1 1.70 max 1.40 0.10 0.10 0 8 m *0.17 0.05 *0.22 0.05 1.25 0.20 0.04 0.15 0.04 figure e.1 package dimensions (fp-144f)
sh7718r hardware manual publication date: 1st edition, september 1998 2nd edition, march 2000 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 1998. all rights reserved. printed in japan.

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